PIC24 MCUs and dsPIC® Digital Signal Controllers (DSCs) share the same modified Harvard Architecture. An embedded processor using a Harvard architecture has separate data and instructions buses.
Simplified Bock Diagram of a PIC24/dsPIC® DSC
- The CPU fetches 24-bit wide instructions from Program Memory over the Instruction bus
- Data Memory and Peripherals operations occur on a separate 16-bit Data bus.
Separate data and instruction buses provide for a deterministic instruction period through the use of a two stage pipeline. One instruction is executed on the data bus while the next instruction if fetched on the instruction bus.
CPU and Instruction Set
PIC24 MCUs and dsPIC DSCs have 24-bit wide flash memory to store program instructions. Each program memory instruction take two even word aligned addresses. The least significant word is assigned the even address. The most significant word is assigned the higher (odd numbered) address. Only the lower 8 bits of the most significant word are implemented. If read, the upper 8-bits of the most significant word will appear as 0.
Program memory is accessed by a 23-bit program counter. When pointing to an instruction, the least significant bit of the program counter will always be 0. While the program counter is capable of addressing up to 4 M instructions, no currently available 16-bit MCU or DSC contains this amount of memory.
- The first 512 Bytes of program memory are used for the reset and interrupt vectors.
- The space for the application program starts at address 0x0200.
- Located at addresses not accessible by the program counter are the Device ID and the device's Configuration Registers
More information on the program memory, including how a program can read and write to on-board flash, can be found on this site's 16-bit Program Memory page.
PIC24 MCUs and dsPIC DSCs can address 64 kBytes of data memory. The amount of data memory available varies from device to device. Only the lower 32 kBytes can be directly populated with RAM. Under program control, the upper 32 kBytes of address space can either point to a section of program memory or extended data memory.
The first 2 kBytes of data memory contains the registers controlling the I/O ports and peripherals.
If a device supports Direct Memory Access (DMA) transfers a dual port buffer in memory is located immediately above the installed data RAM. The DMA control peripheral transfers data between this memory buffer and selected peripherals with minimal CPU intervention.
A full description of the data memory, including details how C compilers use data memory, can be found on the Data Memory page,
Accessing Flash Memory from RAM
Page Space Visibility (PSV) is the process which allows the upper 32 kBytes of data memory addresses to point to a block of flash memory.
Program Space Visibility (PSV) maps selected blocks of flash program memory into the upper 32 KB of data memory space to provide quick access to literal constants and flash based data tables.
A description of how an application can implement PSV is provided on the PSV page.
Extending Data Memory
Extending the data space to allow access to RAM with the upper 32 kBytes. Byte addresses can be accomplished on 16-bit PIC MCUs and DSCs.
- EDS extends the amount of RAM the CPU can access by mapping 32 KB blocks of memory into the upper 32 KB bytes of the Data Memory space
- Only one 32 KB block of EDS memory can be mapped in at a time
- The upper portion of Data Memory space is shared with PSV
- Useful for graphics, USB and communication intense applications
The Extended Data Memory page gives details on using EDS memory.
Accessing the Peripherals
All peripherals and I/O pins are mapped into memory on 16-bit MCU and DSC families. Modifying a peripheral or accessing an I/O pin is accomplished by reading from, or writing to, special functions registers (SFRs). The SFRs are located in the first 2 kBytes of data memory space.
The 16-bit Peripherals page provides explanations and sample code showing how to work with the 16-bit family's peripherals.
Exception Handling (Interrupts and Traps)
16-bit PIC® MCU interrupts have the following characteristics:
- Separate Interrupt vector for each interrupt source
- Preemptive interrupts based upon user selected priority.
- Run-time control to enable, disable, or change the priority of all interrupts
- Alternate vector table to allow all interrupts to be redirected at run-time
- Provisions to support identification and processing of Non Maskable Interrupts (Traps).
A comprehensive discussion of the interrupt process as well as example code can be found on the Interrupt Processing page
MCU Configuration Registers
Configuration Bits - are a collection of binary data located in the flash program memory of a PIC® MCU or dsPIC DSC. Configuration bits are generated by user-written code and become part of the HEX file programmed into the device. Configuration bits are not executable code as they are located at addresses not accessible by the program counter. Configuration bits complete circuitry which enables or disables hardware features of the device.
Configuration bits cannot be modified during run-time.
The Special Features of MCU operation controlled by the configuration bits include:
- System Clocking
- Power Management
- Device Security
The MCU Configuration Page provides details of the configuration bits and code examples of how they can be programmed.
What happens at Reset and Startup?
At start-up, or when a release from Reset occurs, the follow happens:
- All registers revert to their predefined reset state.
- The program counter is cleared which results in executing the instruction at address 0x0000.
By default the MPLAB® XC16 compiler places the start of the user code at address 0x0200 and inserts a GOTO 0x0200 instruction at address 0x0000.
16-bit MCU and DSCs can be reset from several sources. A full explanation of the reset operations, including examples of how to detect anomalous resets can be found in the 16-bit Start-up page.
dsPIC DSCs have the same architecture as a PIC24 but add 19 DSP instructions. Many of these DSP instructions require two operands to be concurrently retrieved from memory. To accommodate the need for dual access of data memory, dsPIC DSCs provide for the data RAM to be split into two regions, each with its own bus.
Simplified Block Diagram of a dsPIC® DSC when Executing a DSP Instruction
When a dsPIC DSC executes a DSP instruction:
- Data memory appears to consist of two regions: X and Y.
- Two data buses are available to concurrently access data memory. One bus accesses the X memory space and the other is dedicated to accessing the Y memory.
- Simultaneous read/modify/write-backs may be executed on both data buses.
When a dsPIC executes one of the 76 MCU commands the data memory appears as one contiguous region accessed by a single data bus.
The dsPIC Architectural Tutorial offers details and example code on how DSCs operate.
Direct Memory Access (DMA)
The DMA controller transfers data between a peripheral's registers and memory. The 16-bit DMA controller uses dual-ported memory and a control scheme which allows transfers to occur with no impact on CPU operation.
The DMA controller supports eight independent channels. Each channel can be configured for transfers to or from selected peripherals. Peripherals supported by the DMA controller include:
- ECAN™ technology
- 10-bit/12-bit Analog-to-Digital Converter (ADC)
- Serial Peripheral Interface (SPI)
- Input Capture
- Output Compare
A description of the DMA structure and sample code showing how to set up and use the DMA can found on the DMA page.