Doze, Idle, and Sleep Mode in 16-bit MCUs and DSCs

Doze, Idle, and Sleep modes allow the system clock to be manipulated by an application in order to reduce power consumption. Sleep has an additional option referred to as Low Voltage Sleep.

Mode CPU Clock
(Fcy)
System Clock
(Fosc)
Peripheral Clock
(Fp)
All Memory Retained
Doze Slower Full Speed Full Speed Yes
Idle Stopped Full Speed Full Speed Yes
Sleep Stopped Stopped Stopped Yes
Low Voltage Sleep Stopped Stopped Stopped Yes

Doze Mode

Doze Mode allows the application program to slow down the CPU clock while leaving the peripheral clock unchanged. When switching to Doze mode no adjustment is needed to the individual peripheral configuration registers. The operation of the peripherals is not effected by the change in the CPU clock speed.

Entering Doze Mode

Doze Mode is controlled by the upper five bits of the Clock Divider Register CLKDIV<15:11>.

  • The Doze Enable (DOZEN) bit causes the device to enter Doze Mode.
  • When DOZEN is set, the speed of the CPU is cycled down by the amount specified by DOZE<2:0>
  • The user has the option of restoring the CPU clock to the speed set by the configuration bits when an interrupt occurs. This allows interrupts to be processed at full speed. The Recover on Interrupt (ROI) bit controls the state of the clock for interrupt processing.

Exiting Doze Mode

Doze Mode is exited by clearing the DOZEN bit.

Idle Mode

Idle mode turns off clock to the CPU, but leaves the clock to the peripherals unchanged. In Idle mode the system oscillator is left running and the data in all memory locations is retained.

Entering Idle Mode

A device is put into Idle mode by executing the PWRSAV assembly instruction with the suffix #1

PWRSAV #1
.
// Alternatively, if the appropriate INC file in .included:

PWRSAV #IDLE_MODE

The MPLAB® XC16 C Compiler defines a macro for PWRSAV #IDLE_MODE

#include <xc.h>

Idle(); // enter Idle mode

Exiting Idle Mode

Idle mode will end and the CPU will execute the instruction immediately following the PWRSAV instruction upon the following conditions:

  • A Reset condition, other than a Power-On Reset.
  • A Watchdog Timer overflow
  • An interrupt request occurs with a priority less than or equal to the current priority of the CPU.

If an interrupt occurs with a priority higher than the present CPU priority, the CPU wakes up and begins execution with the interrupt service routine.

Sleep Mode

Sleep Mode turns off the system clock. (If enabled, the WatchDog Timer WDT will run off the LPRC). The CPU and all peripherals requiring the system clock will cease operation. The contents of the memory and registers are maintained in sleep mode.

Entering Sleep Mode

A device is put into Sleep mode by executing the PWRSAV assembly instruction with the suffix #0

PWRSAV #0
.
// Alternatively, if the appropriate INC file in .included:

PWRSAV #SLEEP_MODE

The MPLAB® XC16 C Compiler defines a macro for PWRSAV #SLEEP_MODE

#include <xc.h>

Sleep(); // enter Idle mode

Exiting Sleep Mode

Sleep Mode will end and the CPU will execute the instruction immediately following the PWRSAV instruction upon the following conditions:

  • A Reset condition, other than a Power-On Reset.
  • A Watchdog Timer overflow
  • Any interrupt request occurs.

Delay in Exiting Sleep Mode

The delay associated with waking up from Sleep will vary depending upon the oscillator mode being used. For most oscillator settings the delay in waking up from Sleep is the same as when the device is first powered on. Please consult the datasheet of the device you are using to determine the specific delay for the part you are using.

Low Voltage Sleep Mode

Low Voltage Sleep mode stops the system clock in the same way as Sleep Mode. Low Voltage Sleep mode uses a low voltage regulator to power the core. Low Voltage Sleep uses less power than Sleep Mode, but takes longer to wake-up from sleep due to the voltage regulator.

Entering Low Voltage Sleep

The low-voltage regulator is controlled by the LPCFG/LVRCFG Configuration bit (also designated as LVRCFG is some devices), and the Low Voltage Enable bit (RETEN/LVREN) Reset and System Control Register (RCON). The LPCFG/LVRCF configuration bit makes the low-voltage regulator available to be controlled by RCON.

With the the LPCFG/LVRCFG configuration bit set, the follow sequence of instructions will put the device into Low Voltage Sleep:

  1. Setting the LVREN bit in RCON
  2. Executing PWRSAV instruction with the suffix #0

// With the appropriate INC file in .included:

BSET RCON LVREN
PWRSAV #SLEEP_MODE

With MPLAB® XC16 C Compiler

#include <xc.h>

RCONbits.LVREN = 1 ;
Sleep(); // enter Idle mode

Exiting Low Voltage Sleep

Low Voltage Sleep Mode will end and the CPU will execute the instruction immediately following the PWRSAV instruction upon the following conditions:

  • A Reset condition, other than a Power-On Reset.
  • A Watchdog Timer overflow
  • Any interrupt request

 Learn More

 
Low Power Operating Modes
Learn more >
 
Deep Sleep
Learn more >
 
Switching Clock Sources
Learn more >
 
Battery Backup (Vbat)
Learn more >

20th Annual
Microchip MASTERs Conference 2016
Register now - Deadline: July 29

JW Marriott Desert Ridge Resort-Phoenix, AZ

© 2016 Microchip Technology, Inc.
Information contained on this site regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.