16-Bit Oscillator System: Auxiliary Oscillator and PLL

Overview

The Auxiliary Oscillator and PLL Block (ACLK) is used by the Universal Serial Bus (USB) module, which needs to operate at a frequency unrelated to the system clock.

auxpll.png

This oscillator is available on select dsPIC33E/PIC24E devices having a USB module.

Detailed Block Diagram

The Auxiliary Oscillator and PLL Block consists of the following sub-systems:

auxpll-complete.png
  • Auxiliary Oscillator
  • Auxiliary PLL Clock Source Select
  • Auxiliary PLL

Auxiliary Oscillator

The ACLK is used by the Universal Serial Bus (USB) module, which needs to operate at a frequency unrelated to the system clock. The auxiliary oscillator can use one of the following as its clock source:

auxpll-aux-osc.png
  • Crystal (XT): Crystal and ceramic resonators in the range of 3.5 MHz - 10 MHz
  • High-Speed Crystal (HS): Crystals in the range of 10 MHz - 40 MHz; the external crystal is connected to the SOSCI and SOSCO pins
  • External Clock (EC): External clock signal up to 60 MHz; the external clock signal is directly applied to the SOSCI pin

Enabling the Auxiliary Oscillator:

To enable the Auxiliary Oscillator mode, the Enable Auxiliary PLL bit (ENAPLL) must be set in the Auxiliary Clock control register (ACLKCONx<15>). The Auxiliary Oscillator Mode bits (AOSCMD<1:0>) allow four oscillator mode settings, as listed in the following table:

auxpll-aux-osc-settings.png

By default, the USB module is clocked by the primary oscillator (POSC) with PLL.

Auxiliary PLL Clock Source

The desired reference clock source for the auxiliary PLL can be selected by setting the appropriate clock source select bits in the Auxiliary Clock Control Register 1 (ACLKCONx).

Set the Auxiliary Reference Clock Select bit (ASRCSEL) to use the primary oscillator as the clock source or clear this bit to use the auxiliary oscillator as the clock source.

Set the FRC Select bit (FRCSEL) to use the FRC as the clock source, or clear this bit to use the auxiliary or primary oscillator selected by the ASRCSEL bit as the clock source.

auxpll-aux-pll-clk-src.png

Auxiliary PLL

For operation of the APLL, the Auxiliary Phase Frequency Detector (APFD) input frequency and the Auxiliary Voltage Controlled Oscillator (AVCO) output frequency must meet the following requirements:

  • The APFD input frequency (AFPLLI) must be in the range of 3 MHz - 5.5 MHz
  • The AVCO output frequency (AFSYS) must be in the range of 60 MHz - 120 MHz

The APLL Phase Detector Input Divider bits (APLLPRE<2:0>) in the Auxiliary Clock Control Register 1 (ACLKCONx<2:0>) specify the input divider ratio (N1), which is used to scale down the Auxiliary PLL Input (AFIN) clock to meet the APFD input frequency range of 3 MHz to 5.5 MHz.

The Auxiliary PLL Feedback Divisor bits (APLLDIV<2:0>) in the Auxiliary Clock Control Register 2 (ACLKDOVx<2:0>) specify the divider ratio (M), which scales down the AVCO frequency (AFSYS) for feedback to the APFD. The AVCO frequency (AFSYS) is M times the APFD input frequency (AFPLLI).

The APLL VCO Output Divider Select bits (APLLPOST<2:0>) in the Auxiliary Clock Control Register 1 (ACLKCONx<7:5>) specify the divider ratio (N2).

The correct combination of the APLL Phase Detector Input Divider bits (APLLPRE<2:0>), the Auxiliary PLL Feedback Divisor bits (APLLDIV<2:0>), and the APLL VCO Output Divider bits (APLLPOST<2:0>) will provide the 48 MHz Auxiliary Clock (ACLK) frequency needed by the USB module.

Set the Select Clock Source to Auxiliary Clock Divider bit (SELACLK) in the Auxiliary Clock Control Register 1 (ACLKCONx) to select the auxiliary PLL or oscillators to provide the clock source for the auxiliary clock divider.

Clearing the SELACLK bit will cause the primary PLL output to act as the clock source to the auxiliary clock divider.

auxpll-aux-pll.png

AFSYS and ACLK Calculation:

The following equations define the relations between the Auxiliary PLL Input (AFIN) clock frequency and the Auxiliary VCO (AVCO) and Auxiliary Clock (ACLK) frequencies.

(1)
\begin{align} AVCO=AF_{SYS} \times (\frac{M}{N_{1}}) \end{align}
(2)
\begin{align} ACLK=AF_{IN} \times (\frac{M}{{N_{1} \times {N_2}}}) \end{align}

Where

N1 = APLLPRE + 1
N2 = APLLPOST + 1
M = APLLDIV + 15

When APLLDIV<2:0> = 111, substitute (APLLDIV + 15) with (APLLDIV + 18) in the above equation.

Code Example: Configure APLL with Auxiliary Oscillator with an 8 MHz XTAL

In this configuration, the 8 MHz XTAL is connected to SOSCI/SOSCO pins. The application firmware must perform the following steps:

  1. Clear the ASRCSEL bit to choose the auxiliary oscillator as the clock source for the APLL.
  2. Clear the FRCSEL bit to choose the auxiliary oscillator at the clock source for the APLL.
  3. Set the SELACLK bit to choose the auxiliary PLL or oscillators to provide the source clock for the auxiliary clock divider.
  4. Follow these steps to configure the APLL Phase Detector Input Divider bits (APLLPRE<2:0>), the Auxiliary PLL feedback Divisor bits (APLLDIV<2:0>) and the APLL VCO Output Divider bits (APLLPOST<2:0>) to set up the APLL for a 48 MHz ACLK (used by the USB module) using an 8 MHz auxiliary oscillator:
    1. Select the APLL VCO output divider to meet the AVCO output frequency requirement (60 MHz < AFSYS < 120 MHz).
      1. Select an APLL VCO output divider ratio of N2 = 2
      2. Ensure that AFSYS = (ACLK x N2) = 96 MHz
    2. Select the APLL phase detector input divider to meet the APFD input frequency requirement (3 MHz < AFPLLI < 5.5 MHz).
      1. Select an APLL phase detector input divider ratio of N1 = 2
      2. Ensure that AFPLLI = (AFIN ÷ N1) = 4 MHz
    3. Select the auxiliary PLL feedback divisor to generate the required VCO output frequency based on the APFD input frequency.
      1. AFSYS = AFPLLI x M
      2. M = AFSYS ÷ AFPLLI = 24
  5. Enable the auxiliary PLL by setting the ENAPLL bit.
#include <xc.h>

// No configuration bit settings are required for the APLL

int main(void)
{
    ...
    // Configure APLL prescaler, APLL postscaler, APLL divisor

    ACLKCON3bits.ASRCSEL = 0; // Select Auxiliary Oscillator as the clock source
    ACLKCON3bits.FRCSEL = 0; // Select Auxiliary Oscillator as the clock source
    ACLKCON3bits.SELACLK = 1; // Select Auxiliary PLL or oscillators to provide

    // the source clock for auxiliary clock divider

    ACLKDIV3bits.APLLDIV = 0b111; // M = 24
    ACLKCON3bits.APLLPRE = 0b001; // N1 = 2
    ACLKCON3bits.APLLPOST = 0b111; // N2 = 2
    ACLKCON3bits.ENAPLL = 1; // Enable Auxiliary Clock
    ...
}

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