The 16-bit PIC® MCU and dsPIC® digital signal controllers (DSCs) oscillator system has multiple internal clocks that are derived from internal or external clock sources. Some of these clock sources have Phase-Locked Loops (PLLs), programmable output divider, and/or an input divider, to scale the input frequency to suit the application.
The CPU clock source can be changed on-the-fly by software. Registers controlling these clocks are locked by hardware to protect against erroneous clock switching. They must be unlocked by a series of writes before software can perform a clock switch.
A Fail-Safe Clock Monitor (FSCM) mechanism detects clock failure and permits safe application recovery or shutdown by using one of the on-chip fast RC oscillators.
The default (hardware power-up) CPU clock source and initial configuration is determined by configuration bit settings. Additional configuration may be set at run-time.
Additionally, one or more MCU pins are available for outputting the instruction clock and/or a scaled primary oscillator clock signal.