16-Bit Oscillator System: 24x (96 MHz) PLL

24x (96 MHz) PLL (PIC24F GB, DA)

For PIC24F devices with USB features (such as the PIC24FJ256GB110 family) and graphics controller features (such as the PIC24FJ256DA210 family), a 96 MHz PLL block is implemented to generate the stable 48 MHz clock required for full-speed USB operation, a programmable clock output for the graphics controller module and the system clock from the same oscillator source.

The 96 MHz PLL block requires a 4 MHz input signal; it uses this to generate a 96 MHz signal from a fixed, 24 x PLL. This is, in turn, divided into three branches. The first branch generates the USB clock, the second branch generates the system clock and the third branch generates the graphics clock.

The 96 MHz PLL prescaler does not automatically sense the incoming oscillator frequency. The user must manually configure the PLL divider to generate the required 4 MHz output, using the PLLDIV<2:0> Configuration bits (Configuration Word 2 <14:12> in most devices).


Code Example:

The following MPLAB® XC16 code example enables the 96 MHz PLL with Primary OSC (HS) as the default system clock for a PIC24FJ256GB110 USB MCU. The MCU has an external 12 MHz crystal on OSC1/OSC2. With the default CPDIV<1:0> settings, this produces a 32 MHz system clock (16 MIPs operation).

#include <xc.h>

#pragma config FNOSC = PRIPLL      // default System clock = Primary OSC with 24x PLL module
#pragma config POSCMOD = HS    // configure POSC for 12 MHz crystal input
#pragma config PLLDIV = DIV3    // divide POSC to get 4 MHz input to PLL
#pragma config PLL_96MHZ = ON    // enable the 96MHz PLL

int main(void)

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