16-Bit Oscillator System: 80 MHz PLL

80 MHz PLL (dsPIC33F/PIC24H)

dsPIC33F and PIC24H devices contain a programmable PLL module which can be used to provide an FOSC = 80 MHz (max.) system clock, enabling an FCY = 40 MIPs (max.) operation.

The 80 MHz PLL block requires a 0.8-8 MHz input signal; it uses this to generate a 100-200 MHz output signal which is then scaled to provide an 80 MHz (max.) system clock.

80mhzpll.png

For a proper PLL operation, the Phase Frequency Detector (PFD) input frequency, FREF, and Voltage Controlled Oscillator (VCO) output frequency, FVCO, must meet the following requirements at all times:

  • FREF must be in the range of 0.8-8 MHz
  • FVCO must be in the range of 100-200 MHz

PLL register default settings on POR place certain constraints on application code for oscillator configuration. These are discussed below.

PLL Configuration:

PLL frequency control is achieved via dynamic SFR register modification:

  • CLKDIV<PLLPRE4:0> - specify the input frequency divider ratio (N1)
  • CLKDIV<PLLPOST1:0> - specify the output frequency divider ratio (N2)
  • PLLFBD<PLLDIV8:0> - specify the divider ratio (M)

The following equations define the relations between FIN, FREF, FVCO, FOSC:

(1)
\begin{align} {F_{REF}=\frac{F_{IN}}{N_{1}}} , \; F_{VCO}=F_{IN} \times (\frac{M}{N_{1}}) , \; F_{OSC}=F_{IN} \times (\frac{M}{{N_{1}}\times {N_{2}}}) \end{align}

Where

N1 = PLLPRE+2
N2 = 2 x (PLLPOST + 1)
M = PLLDIV + 2

Input Clock Limitation at Start-up:

Default POR values of PLLPRE, PLLPOST and PLLDIV, set N1=2, N2=4 and M=50 respectively.

Given these reset values, the following relations are active at POR:

(2)
\begin{align} F_{REF}=0.5 \times F_{IN},\; F_{VCO}=25 \times F_{IN}, \; F_{OSC}=6.25 \times F_{IN} \end{align}

Given the preceding equations, the FIN to the PLL module must be limited to 4 MHz < FIN < 8 MHz to comply with the FVCO requirement (100 MHz < FVCO < 200 MHz), if the default values of PLLPRE, PLLPOST, and PLLDIV are used.

To use a PLL when the input frequency is not within the 4-8 MHz range, you must follow this process:
1. Power-up the device with the Internal FRC Oscillator, or the POSC, without a PLL.
2. Change PLLDIV, PLLPRE, and PLLPOST bit values, based on the input frequency, to meet these PLL requirements:

  • FREF must be in the range of 0.8-8.0 MHz
  • FVCO must be in the range of 100-200 MHz

3. Switch the clock to a PLL mode in software.

PLL Lock Status:

Whenever the PLL input frequency, the PLL prescaler, or the PLL feedback divisor, is changed, the PLL requires a finite amount of time (TLOCK) to synchronize to the new settings.

TLOCK is applied when the PLL is selected as the clock source at a POR, or during a clock switching operation. The value of TLOCK is relative to the time at which the clock is available to the PLL input. For example, with the POSC, TLOCK starts after the OST delay. Refer to the specific device data sheet for information about typical TLOCK values.

The LOCK bit in the Oscillator Control register (OSCCON<5>) is a read-only Status bit that indicates the lock status of the PLL. The LOCK bit is cleared at a POR, and on a clock switch operation, if the PLL is selected as the destination clock source. The LOCK bit remains clear when any clock source that is not using a PLL is selected. After a clock switch event in which a PLL is enabled, it is a good practice to wait for the LOCK bit to be set before executing other code.

Code Example: Configure dsPIC33F for 40 MIPs Operation with POSC = 8 MHz XTAL

In this configuration, the POSC input frequency (FIN) complies with the default PLL divisor settings to meet the FVCO requirements (4 MHz < FIN < 8 MHz), however, it is unable to meet the user requirements (FCY = FOSC/2 = (6.25 x FIN)/2 = 25 MIPs) with these settings.

We will need to enable a non-PLL oscillator type on POR (ex. 7.37 MHz FRC), perform the correct PLL adjustments in our application code, then initiate a clock switch to the PLL:

#include <xc.h>

#pragma config FNOSC = FRC      // select internal FRC at POR
#pragma config FCKSM = CSECMD    // enable clock switching
#pragma config POSCMD = XT    // configure POSC for XT mode

int main(void)
{
    // Configure PLL prescaler, PLL postscaler, PLL divisor
    PLLFBD=41; // M = 43
    CLKDIVbits.PLLPOST = 0; // N2 = 2
    CLKDIVbits.PLLPRE = 0; // N1 = 2

    // Initiate Clock Switch to Primary Oscillator with PLL (NOSC = 0b011)
    __builtin_write_OSCCONH(0x03);
    __builtin_write_OSCCONL(0x01);

    // Wait for Clock switch to occur
    while (OSCCONbits.COSC != 0b011);

    // Wait for PLL to lock
    while(OSCCONbits.LOCK != 1);    

    ...
}

The PLL Prescaler (PLLPRE) and PLL Feedback Divisor (PLLDIV) bits should not be changed when operating in PLL mode. You must clock switch to a non-PLL mode (e.g., Internal FRC) to make the necessary changes and then clock switch back to the PLL mode.

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