To initialize the PTG the following steps should be considered:
- Initialization of the other MCU peripherals
- Accessing the PTG Registers
- Initializing the Limit, Hold and Adjust registers
- Establishing Step Command Timing
Initialize the MCU Peripherals
The Peripheral Trigger Generator (PTG) coordinates and sequences events between selected peripherals. The PTG works with the Analog-to-Digital Converter, the Output Compare/PWM module, all General Purpose Timers and the MCU's Interrupt Controller.
The mechanisms used to coordinate peripheral activities are triggers and interrupt requests (IRQs). The PTG can be programmed to either output a trigger, or to generate a PTG IRQ, based upon a trigger received from another peripheral. Successful sequencing depends upon careful coordination of the initialization of the PTG and PTG-monitored peripherals. Peripherals used in PTG sequences must be programmed to accept the appropriate PTG trigger(s) and, when needed, send a trigger to the PTG .
Example of Coordinating Trigger Assignments
The PTG on the dsPIC33EP256GP506 is capable of sending a trigger to the Output Compare (OC) module. This PTG-generated trigger can serve as the OC module's clock or sync signal. The OC module can also generate a trigger signal for the PTG to monitor. The OC module generated trigger is seen by the PTG as either OC1 or OC2 trigger.
To allow a PTG generated trigger to be the clock source for the OC module, OCxCON1 must be programmed.
OCxCON2 can be programmed to allow a PTG generated trigger to synchronize the OC module. For sequences in which the PTG generates IRQ, it is imperative that the MCU's interrupt controller be initialized so that the PTG IRQs are enabled.
Please consult the datasheet for the MCU you are using to verify the initialization requirements.
Accessing PTG Registers
In addition to the registers needed to implement the queue, the Peripheral Trigger Generator (PTG) is controlled by twelve Special Function Registers (SFRs). Although initializing twelve SFRs may appear a daunting task, it is important to realize that not all of the SFRs may need to be initialized. The default settings for the PTG SFRs are non-intrusive. If an SFR controls a parameter not specifically used in a sequence, that SFR does not need to be initialized for the sequence to execute properly.
The PTG SFRs are divided into five categories:
Control and Status Registers
|PTGCST||Provides overall control and status reporting for the PTG including Enable/Disable, Start/Stop , and Trigger output type (Toggle or Pulse). This is the only register which can be accessed while the PTG is enabled.|
|PTGCON||Determines the values used for many of the PTG timing parameters include the clock source, any prescalers on the clock, and the width of the output triggers when the triggers are in pulse mode. This registers also control the value of the PTG's watchdog timer. which limits the time the PTG will wait for a trigger.|
|PTGT0LIM||Determines the limit value for PTG Timer 0. Used by PTGCTRL to delay or pause the sequence|
|PTGT1LIM||Determines the limit value for PTG Timer 1. Used by PTGCTRL to delay or pause the sequence|
|PTGSDLIM||Sets the number of PTG clock cycles allocated to each step command. Using this register can slowdown the speed in which PTG Step commands are executed. The use of this Delay timer can be enabled or disabled with the PTGCTRL command|
|PTGC0LIM||Used to specify the loop count for the PTGJMP0 command.|
|PTGC1LIM||Used to specify the loop count for the PTGJMP1 command|
Hold and Adjust Registers
|PTGHOLD||Used by the PTGCOPY command this register hold the value to be moved into one of the Limit registers, or into the PTG Literal register (PTGL0)|
|PTGADJ||Used by the PTGADD command this register hold a value to be added to one of the Limit registers, or the PTG Literal register (PTGL0)|
Literal and Broadcast Registers
|PTGL0||Holds a value to be written into the ADC1 channel select register (AD1CHS0). Only used by the PTGCTRL command. AD1CHS0 can also be written with the PTGSTRB commnad.|
|PTGBTE||When the application wishes to simultaneously broadcast triggers to more than one peripheral (PTGCTRL command with OPTION = 0b1111) this register contains the list of triggers to generate.|
PTG Queue Registers
|PTGQPTR||Points to the current Step Commnad being executed. When the PTG is enabled this register is set to the first entry in the Step queue|
|These registers are the queue in which the Step commands are located.|
To prevent unintentional modifications to PTG operations caused by spurious writes to the PTG SFRs, the PTG Status and Control Register PTGCST is the only register which can be written to while the PTG is enabled. To modify PTG SFRs other than PTGCST you must ensure that the PTG is disabled (i.e. verify PTGCST<15> = 0).
Initializing the Limit, Hold, and Adjust Registers
Limit registers are used by Step Commands to control sequence timing.
PTGT0LIM and PTGT1LIM are used to insert one-time pauses into a sequence. The Peripheral Trigger Generator control (PTGCTRL) Step command has an option which will start either PTG Timer0 or PTG Timer1, then wait until the value of the timer equals the value of its limit register. When the values equal each other, control is passed to the next Step Command in the queue.
PTGSDLIM (Step Delay Limit register) is used to insert a temporary and repeatable delay for every Step Command in a sequence. The value loaded into PTGSDLIM is the number of PTG clocks needed to execute a single Step Command. When enabled, PTGSDLIM will cause the time period between successive Step Commands to be longer. When this register is disabled, all Step Commands will execute at the speed of the designated PTG clock. PTGSDLIM can be enabled or disabled using an option of the PTGCTRL Step Command.
PTGC0LIM and PTGC1LIM are loop counters for the conditional jump commands ( PTGJMPC0 and PTGJMPC1). Using two loop counters allows a single level of nesting.
Example of a Nested Loop using the PTGCxLIM registers
In this example if PTGC0LIM = 3, and PTGC1LIM = 8 then the following commands would be executed before control is passed to the command in Step 5:
- The Step Command loaded into Step 1 will execute 24 (3 x 8) times.
- The Step Command loaded into Step 3 will execute 8 times.
- All Limit registers can be initialized with a simple assignment statement when the PTG is disabled. (e.g. PTGSDLIM = 7;)
- During run-time the value of any limit register can be modified by the use of PTGCOPY or PTGADD Step commands.
The PTGADD Step Command will add the value of the literal stored in PTGADJ to a limit register. (The particular limit register to be modified is passed in the command's OPTION field.) Modifying the limit registers allows sequences to incrementally adjust the timing of generated triggers.
The PTGCOPY Step command moves the content of PTGHOLD into any of the limit registers. PTGCOPY is typically used to reset a limit register to its initial value after the limit register has been modified by PTGADD.