Extreme Low Power Modes of 16-bit PIC® MCUs

Deep Sleep

Deep Sleep is the lowest power sleep mode for Microchip's MCUs and DSCs. This mode is intended to extend battery life by minimizing power consumption during inactive periods.

In Deep Sleep the system clock source and all the peripherals except the Real Time Calendar Clock (RTCC) and Deep Sleep Watchdog timer (DSWDT) are disabled. (In devices with XLP technology the DSWDT and RTCC have their own independent clock sources.)

Deep Sleep can be entered with the option of retaining the contents of the memory. If this retention option is used, all the memory content is retained and execution resumes at the instruction immediately following the Sleep command. If the retention option is not used only the two Deep Sleep retention registers (DSGPR0 and DSGPR1) are maintained. All other memory is lost. Exiting Deep Sleep without the retention option causes the MCU to begin executing at the reset vector.

Mode System Clock How Much Memory
is Maintained
Exit Location
Deep Sleep
With Retention
OFF 100% Next Instruction
Deep Sleep
Without Retention
OFF Two Registers Reset Vector

Deep Sleep Mode is not available on all 16-bit MCUs and DSCs. Only devices with Microchip's eXtreme Low Power (XLP) technology support Deep Sleep. Please consult the data sheet of the device you are using to ensure support of Deep Sleep.

Entering Deep Sleep Mode - Without Memory Retention Set

To enter Deep Sleep mode without memory retention the following sequence must occur:

  • The Deep Sleep Enable (DSEN) bit in the Deep Sleep Control Register DSCON must be set.
  • Executing the SLEEP instruction with one to three instruction cycles of setting DSEN

In order to minimize the possibility of inadvertently entering Deep Sleep, the DSEN bit is cleared in hardware after five instruction cycles have elapsed. In order to enter Deep Sleep, the SLEEP instruction must be executed within one to three instruction cycle after setting DSEN. If DSEN is not set when Sleep is executed, the device will enter conventional Sleep mode
instead.

To further minimize the possibility of inadvertently entering Deep Sleep, to set a bit in the Deep Sleep Control register the write instruction MUST be executed twice. This is referred to as the Repeat Sequence.

// If the appropriate INC file in .included:

BSET DSCON DSEN
NOP Writes to the DSEN bit do not need
NOP to be sequential (back-to-back)

BSET DSCON DSEN

PWRSAV #SLEEP_MODE;

The MPLAB® XC16 C Compiler has no pre-defined macros for entering Deep Sleep with or without memory retention.

Entering Deep Sleep Mode - With Memory Retention

Deep Sleep with memory retention requires the use of the on-chip Low Voltage Regulator. The low-voltage regulator is controlled by the LPCFG/LVRCFG Configuration bit (also designated as LVRCFG is some devices), and the Low Voltage Enable bit (RETEN/LVREN) Reset and System Control Register (RCON). The LPCFG/LVRCF configuration bit makes the low-voltage regulator available to be controlled by RCON.

With the configuration bits set, to enter Deep Sleep mode with memory retention the following ordered sequence of event must occur:

  • The Low Voltage Regulator Enable bit (RETEN/LVREN) in the Reset and System Control Register (RCON) must be set.
  • The Deep Sleep Enable (DSEN) bit in the Deep Sleep Control Register (DSCON) must be set. (Setting DSEN requires the write instruction be executed twice.)
  • Executing the SLEEP instruction with one to three instruction cycles of setting DSEN

// If the appropriate INC file in .included:
BSET RCON LVREN

BSET DSCON DSEN
NOP Writes to the DSEN bit do not need
NOP to be sequential (back-to-back)

BSET DSCON DSEN

PWRSAV #SLEEP_MODE;

The MPLAB® XC16 C Compiler has no pre-defined macros for entering Deep Sleep with or without memory retention.

Exiting Deep Sleep Mode

The device can be awakened from Deep Sleep modes by any of the following:

  • Master Clear (MCLR) event
  • Power On Reset
  • RTCC alarm
  • INT0 interrupt
  • I/O pin interrupt
  • DSWDT event

The software can determine the wake-up event source by reading the DSWAKE register. The contents of DSWAKE is cleared by hardware when entering Deep Sleep mode, so software can read this register anytime after waking up.

The application software may need to check DSGPR0 and DSGPR1 to verify what steps need to be accomplished in order to restore the state of the system.

Does using the Retention mode of Deep Sleep Always Use More Power?

When calculating total power consumption (Ptotal) one must add the power consumed in the Active state (Pactive) to the power consumed in the Sleep State (Psleep).

Ptotal = Pactive + Psleep

Deep Sleep without memory retention will always use less Psleep but may not use less total power. Waking up at the reset vector requires the MCU to execute more instructions than waking up at the next instruction. The extra power used during the wake-up period of non-retained Deep Sleep can offset the lower Psleep IF the interval between the wake-up events too short. When using Deep Sleep mode check your total power usage and sleep intervals before you forgo retaining the memory.

 Learn More

 
Doze, Idle and Sleep Modes
Learn more >
 
Battery Backup
Learn more >
 
Switching Clock Sources
Learn more >
 
Low Power Operating Modes
Learn more >

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