Cortex®-M0+ Nested Vector Interrupt Controller

The ARM® Cortex®-M0+ Nested Vector Interrupt Controller (NVIC) provides an interface between interrupt sources external to the core (peripherals and external pins), and the core.

The priority for each interrupt source is programmable (four levels). If two pending interrupts share the same priority, priority is given to the interrupt with the lowest exception number (lowest interrupt vector address).

The core's 24-bit SysTick system timer can also be used to generate interrupts.

Click image to enlarge.

Each of the interrupt lines is connected to one peripheral instance. Each peripheral can have one or more interrupt flags, located in the peripheral’s Interrupt Flag Status and Clear (INTFLAG) register. The interrupt flag is set when the interrupt condition occurs. Each interrupt in the peripheral can be individually enabled by writing a one to the corresponding bit in the peripheral’s Interrupt Enable Set (INTENSET) register, and disabled by writing a one to the corresponding bit in the peripheral’s Interrupt Enable Clear (INTENCLR) register.

An interrupt request is generated from the peripheral when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt requests for one peripheral are ORed together on system level, generating one interrupt request for each peripheral. An interrupt request will set the corresponding interrupt pending bit in the NVIC interrupt pending registers (SETPEND/CLRPEND bits in ISPR/ICPR). For the NVIC to activate the interrupt, it must be enabled in the NVIC interrupt enable register (SETENA/CLRENA bits in ISER/ICER). The NVIC interrupt priority registers IPR0-IPR7 provide a priority field for each interrupt.

All I/O pins are configured as general purpose I/O (GPIO) by default. Alternatively, these pins can be configured as External Interrupt pins (EXTINT[15:0] & NMI). The External Interrupt Controller (EIC) allows you to configure each interrupt line individually:

  • Edge-sensitive mode (rising, falling, both)
  • Edge-sensitive mode with majority vote filter
  • Level-sensitive mode (high, low)
  • Level-sensitive mode with majority vote filter

When the interrupt has been cleared in edge-sensitive mode, INTFLAG.EXTINT[x] will only be set if a new interrupt condition is met. In level-sensitive mode, when interrupt has been cleared, INTFLAG.EXTINT[x] will be set immediately if the EXTINTx pin still matches the interrupt condition.

The EIC must be enabled to use External Interrupt pins. Note using the NMI (non-maskable interrupt) pin does not require the EIC to be enabled. The NMI interrupt can be disabled by clearing the NMISENSE[2:0] bits in the NMICTRL register.

Each external pin can also be configured to be asynchronous in order to wake up the device from sleep modes where all clocks have been disabled. External pins can also generate an event.

A separate non-maskable interrupt (NMI) is also supported. It has properties similar to the other external interrupts, but is connected to the NMI request of the CPU, enabling it to interrupt any other interrupt mode.

The EIC has one common interrupt request line for all the interrupt sources (except the NMI interrupt request line). You must read the INTFLAG (or NMIFLAG) register to determine which interrupt condition is present.

In addition to generating interrupts, the EIC can also generate an event (External event from pin (EXTINTx)). The Event System (EVSYS) allows autonomous, low-latency and configurable communication between peripherals, without CPU intervention.

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