ARM Cortex®-M0+ Pipeline

The ARM® Cortex®-M0+ core has a two stage pipeline (Cortex-M0, M3 and M4 have three stages). This two stage pipeline decreases the core response time and power consumption.

  • Stage 1: Fetch & Pre-decode
  • Stage 2: Main decode & Execute
pipeline.png

When older Cortex-M cores (with a three stage pipe) execute a conditional branch, the next instructions are no longer valid. This means that the pipeline must be flushed everytime there is a branch. By moving to a two stage pipeline, access to Flash is minimized and power consumption is lowered. Flash memory power often contributes the majority of the power consumed in a microcontroller, so any reduction in Flash accesses has a very direct effect on the total power consumed.

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