Cortex®-M0+ Single Cycle IOBUS

The Arm® Cortex®-M0+ CPU's local bus (IOBUS) provides a direct connection between the CPU and the PORT. IOBUS transactions bypass the Advanced High-performance Bus (AHB) bus allowing I/O pins to be manipulated in a single instruction cycle. IOBUS transactions are not subject to any wait-states induced by AHB bus arbitration.


The IOBUS is used when the CPU performs read or write from address 0x60000000. There are no user-supplied initialization or configuration settings needed to use the IOBUS. The default mode of the MPLAB® XC32 compiler is to use the IOBUS for all digital I/O.

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Using the IOBUS
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Example Project
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