SAM D21 Processor Overview

Cortex M0+ Processor

The SAM D21 implements the ARM® Cortex®-M0+ processor, based on the ARMv6-M Architecture and Thumb®-2 ISA. The Cortex M0+ is 100% instruction set compatible with its predecessor, the Cortex-M0 core, and upward compatible to Cortex-M3 and M4 cores. The ARM Cortex-M0+ implemented is revision r0p1.

For more information, refer to the following documents available from the Arm infocenter:

ARMv6-M Architecture Reference Manual

The ARMv6-M Architecture Reference Manual gives the specification of the architecture on which the Cortex M0+ is based. It covers detailed information about the programmer's model.

Cortex-M0+ Devices Generic Users Guide

The Cortex-M0+ Devices Generic Users Guide is targeted for application software developers, it provides information on the programmer's model, details on using the core peripherals such as NVIC, and general information about the instruction set.

Cortex-M0+ Technical Reference Manual

The Cortex-M0+ Technical Reference Manual is targeted for silicon designers, this document contains implementation-specific information, such as instruction timing, and some of the interface information.

Cortex M0+ Configuration

Table 1 shows the configurable options for the core and which options are enabled for the SAM D21 implementation:

Table 1


Cortex M0+ Core Peripherals

System Control Space (SCS)

The processor provides debug through registers in the SCS. Refer to the "Cortex-M0+ Technical Reference Manual" for details.

System Timer (SysTick)

The [| System Timer (SysTick)]] is a 24-bit timer that extends the functionality of both the processor and the NVIC. Refer to "System Timer (SysTick) Overview" and the "Cortex-M0+ Technical Reference Manual" for details.

Nested Vectored Interrupt Controller (NVIC)

External interrupt signals connect to the NVIC and the NVIC prioritizes the interrupts. The software can set the priority of each interrupt. The Nested Vectored Interrupt Controller (NVIC) and the Cortex-M0+ processor core are closely coupled, providing low latency interrupt processing and efficient processing of late arriving interrupts. Refer to the "Cortex-M0+ Technical Reference Manual" for details.

Single-Cycle I/O Port (IOPORT)

The Cortex-M0+ processor implements a dedicated, single-cycle I/O port bus for high-speed, single-cycle access to peripherals. The single-cycle I/O port is memory mapped and supports all the load and store instructions. This bus is used on SAM D21 to provide single-cycle access to the GPIO ports.

System Control Block (SCB)

The System Control Block provides system implementation information and system control. This includes configuration, control, and reporting of the system exceptions. Refer to the "Cortex-M0+ Devices Generic Users Guide" for details.

Micro Trace Buffer (MTB)

The CoreSight MTB-M0+ (MTB) provides a simple execution trace capability to the Cortex-M0+ processor. Refer to the "CoreSight MTB-M0+ Technical Reference Manual" for details.

© 2024 Microchip Technology, Inc.
Notice: ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries.
Information contained on this site regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.