The System Control Block (SCB) is the programmer's model interface to the processor. It provides system implementation information and system control, including configuration, control, and reporting of system exceptions. The SCB registers are:
Address | Name | Type | Reset value | Description |
---|---|---|---|---|
0xE000ED00 | CPUID | RO | 0x410CC601a | CPUID Register |
0xE000ED04 | ICSR | RWb | 0x00000000 | Interrupt Control and State Register |
0xE000ED08 | VTORc | RW | 0x00000000 | Vector Table Offset Register |
0xE000ED0C | AIRCR | RWb | 0xFA050000 | Application Interrupt and Reset Control Register |
0xE000ED10 | SCR | RW | 0x00000000 | System Control Register |
0xE000ED14 | CCR | RO | 0x00000204 | Configuration and Control Register |
0xE000ED1C | SHPR2 | RW | 0x00000000 | System Handler Priority Register 2 |
0xE000ED20 | SHPR3 | RW | 0x00000000 | System Handler Priority Register 3 |
CPUID Register
The CPUID register contains the processor part number, version, and implementation information.
Interrupt Control and State Register
- The ICSR provides:
- A set-pending bit for the Non-Maskable Interrupt (NMI) exception.
- Set-pending and clear-pending bits for the PendSV and SysTick exceptions
- The ICSR indicates:
- The exception number of the highest priority pending exception.
Vector Table Offset Register
If implemented, the VTOR indicates the offset of the vector table base address from memory address 0x00000000.
Application Interrupt and Reset Control Register
The AIRCR provides endian status for data accesses and reset control of the system.
System Control Register
The SCR controls features of entry to and exit from low power state.
Configuration and Control Register
The CCR is a read-only register and indicates some aspects of the behavior of the Arm® Cortex®-M0+ processor.
System Handler Priority Registers
The SHPR2-SHPR3 registers set the priority level (0 to 192) of the system exception handlers that have configurable priority.
SHPR2-SHPR3 are word accessible.
Ensure software uses aligned 32-bit word size transactions to access all the SCB registers.