SAM D21 System Timer (SysTick)

The SAM D21 ARM® Cortex®-M0+ Processor Core includes an optional system timer (SysTick) that provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism:

This hardware may be configured to periodically generate an interrupt and trigger the following handler routine:

void SysTick_Handler(void){
...
}

SysTick operation is specified in Section B3.3 of the "ARMv6-M Architecture Reference Manual."

SysTick Operation

The system timer consists of four registers (CTRL, LOAD, VAL, CALIB) which are defined in the CMSIS-Core header file core_cm0plus.h. These registers are located in the SAM D21 System Control Space (SCS) memory region, beginning at address 0xE000E010.

These registers are accessed in C via indirect (pointer) access, using the symbol "SysTick" as a base address pointer to the register set, i.e.,

SysTick->CTRL = 0; // Disable SysTick
SysTick->LOAD = 0x0000FFFF; // Set reload value register 
SysTick->VAL = 0; // Reset the counter current value register value

When enabled, the 24-bit timer counter counts down from the value in VAL. When the counter reaches zero, it reloads the value in LOAD on the next clock edge. It then decrements on subsequent clocks. This reloading when the counter reaches zero is called wrapping. When the counter transitions to zero, it sets the COUNTFLAG status bit to 1. If the TICKINT bit is set, an exception may be generated. Reading the COUNTFLAG status bit clears it to 0.

Therefore, the SysTick Interrupt Time Period = (LOAD + 1) * CLK Period.

Writing to VAL clears both the register and the COUNTFLAG status bit to zero. This causes the SysTick logic to reload VAL from LOAD on the next timer clock. A write to VAL does not trigger the SysTick exception logic.

Reading VAL returns the value of the counter at the time the register is accessed. Writing a value of zero to LOAD disables the counter on the next wrap. The SysTick counter logic maintains this counter value of zero after the wrap.

The 24-bit counter is clocked by either the CPU clock (AHB clock) or an implementation-defined Reference Clock. The clock source is set by the CLKSOURCE and NOREF flag bits.

Current SAM D21 errata indicate that the Reference Clock is un-implemented and that the user should configure the SysTick clock source to be the CPU Clock (CLKSOURCE==1).

SysTick Registers

SysTick_CTRL

SysTick_CTRL is a control and status register which configures the SysTick clock, enables the counter, enables the SysTick interrupt, and indicates the counter status.

bit 16

COUNTFLAG: Indicates whether the counter has counted to 0 since the last read of this register.

1 = timer has counted to 0
0 = timer has not counted to 0

COUNTFLAG is set to 1 by a count transition from 1 to 0.
COUNTFLAG is cleared to 0 by a read of this register, and by any write to the Current Value register.

bit 2

CLKSOURCE: Indicates the SysTick clock source.

1 = SysTick uses the processor clock
0 = SysTick uses the optional external reference clock

If no reference clock is provided, this bit reads as one and ignores writes.

bit 1

TICKINT: Indicates whether counting to 0 causes the status of the SysTick exception to change to pending.

1 = count to 0 changes the SysTick exception status to pending
0 = count to 0 does not affect the SysTick exception status

Changing the value of the counter to 0 by writing zero to the SysTick Current Value register (SysTick_VAL) to 0 never changes the status of the SysTick exception.

bit 0

ENABLE: Indicates the enabled status of the SysTick counter.

1 = counter is operating
0 = counter is disabled

SysTick_LOAD

SysTick_LOAD is a counter (re)-load value register.This provides the wrap value for the counter.

bit 23:0

RELOAD: The 24-bit value to (re)-load into the current value register (SysTick_VAL) when the counter reaches 0.

Make sure to load this register with 1 less than the actual # ticks in a desired period, i.e.,

SysTick-->LOAD = ticks -1;

SysTick_VAL

SysTick_VAL is the counter current value register.

bit 23:0

CURRENT: Current counter value. This is the value of the counter at the time it is sampled.

SysTick_CALIB

SysTick_CALIB is calibration value register. This indicates the preload value required for a 10ms system clock.

bit 31

NOREF: Indicates whether an IMPLEMENTATION DEFINED reference clock is provided.

1 = the reference clock is not implemented
0 = the reference clock is implemented

When this bit is 1, the CLKSOURCE bit of the SysTick_CTRL register is forced to 1 and cannot be cleared to 0.

bit 30

SKEW: Indicates whether the 10ms calibration value is exact.

1 = 10ms calibration value is inexact, because of the clock frequency
0 = 10ms calibration value is exact

bit 23:0

TENMS: Optionally, holds a reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. If this field is zero, the calibration value is not known.

SysTick Initialization

As the Reload and Current Value registers are undefined at reset, the SysTick setup code needs to be written in a certain sequence:

Disable the SysTick module
Program the Reload Register
Clear the Current Value Register
Enable the SysTick Module

The following example initializes the SysTick Module to generate interrupt requests every millisecond, given a CPU Clock of 1 MHz:

// Configure SysTick to trigger every millisecond using the CPU Clock
SysTick->CTRL = 0;                    // Disable the SysTick Module
SysTick->LOAD = 999UL;                // Set the Reload Register for 1mS interrupts
NVIC_SetPriority(SysTick_IRQn, 3);    // Set the interrupt priority to least urgency
SysTick->VAL = 0;                    // Clear the Current Value register
SysTick->CTRL = 0x00000007;        // Enable SysTick, Enable SysTick Exceptions, Use CPU Clock
NVIC_EnableIRQ(SysTick_IRQn);        // Enable the SysTick Interrupt (Global)