SAM L10/L11 Clock System

Clock Distribution Overview

The SAM L10/L11 clock system configuration is done through the Oscillator Controller (OSCCTRL), the 32 kHz Oscillator Controller (OSC32KCTRL), the Generic Clock Controller (GCLK) and the Main Clock (MCLK).


Related Peripherals

Clock Controllers and Clock Features:

Clock Sources Controllers (OSCCTRL & OSC32KCTRL)

  • The OSCCTRL controls all the clock sources which are:
    • 0.4-32 MHz Crystal Oscillator (XOSC)
      • Tunable gain control
      • Programmable start-up time
      • Crystal or external input clock on XIN pin
      • Clock failure detection with safe clock switch
      • Clock failure event output
    • 16 MHz Internal Oscillator (OSC16M)
      • Fast startup
      • 4/8/12/16 MHz output frequencies available
    • Ultra-Low Power Digital Frequency Locked Loop (DFLLULP)
      • Operates as a frequency multiplier against a known frequency in closed-loop mode
      • Optional frequency dithering
    • Fractional Digital Phase Locked Loop (FDPLL96M)
      • 48 MHz to 96 MHz output frequency
      • 32 kHz to 2 MHz reference clock
      • A selection of sources for the reference clock
      • Adjustable proportional integral controller Fractional part used to achieve 1/16th of reference clock step
  • The OSC32KCTRL controls the 32 KHz clock sources which are:
    • XOSC32K
      • External 32.768 kHz oscillator
      • 32.768 kHz crystal or external clock
    • OSCULP32K
      • Ultra-low power internal 32.768 kHz oscillator
      • Always ON
      • Frequency fine tuning

In addtion to these features, each clock source controller has the Run in StandBy and the On Demand Clock Request capabilities, refer to the Peripheral Clock Request and Run in StandBy Capability section in this page for more details.

Generic Clock Controller (GCLK):

  • The GCLK controls the clock distribution of the system by implementing the following features:
    • Five GCLK Generators (GCLK0 to GCLK4) to source up to 64 Peripheral Clock Channels (GCLK_PERIPH).
    • Each GCLK Generator has a prescaler to divide internal or external clock sources.
    • The Generic Clock Generator 0 provides the GCLKMAIN which is the clock used to generate synchronous clocks.
    • One GCLK_IO pin for each generator can be used as a clock source for the GCLK or outputs a clock signal to the external world.

Main Clock Controller (MCLK):

  • The MCLK controller generates:
    • CPU, AHB, and APB system clocks
    • Safe run-time clock switching from GCLK
    • Module-level clock gating through maskable peripheral clocks


The Clock system implements two types of clock paths:

  • Asynchronous to the CPU Clock path
  • Synchronous to the CPU clock path

Generic clocks are considered as asynchronous clocks as it can come from different clock sources, whereas CPU and bus clocks (coming from the MCLK) are considered as synchronous to the CPU.

As a consequence, some peripherals accessed by the CPU need to be synchronized between the different clock domains.

Refer to the Asynchronous and Synchronous clock path section in this page.

Generic clocks are typically input clocks of the peripheral. As you can see in this block diagram, the peripheral clocks are fully independent, giving them maximum flexibility.

Clock-Tree Reset State


(*): At reset OSC16M is enabled and configured to run at 4 MHz.

Full Speed (32 MHz) Clock Configuration Example

This example shows the usual configuration to clock the device to its maximum speed (32 MHz) using the FDPLL96MHz. The clock source is XOSC32K but it can be another one.


You can find an example on how to configure the device at full speed below.
You will also find several code snippet examples below.

Code snippet Example: How to configure the Device at full speed using the DPLL96MHz

How to Configure Clocks for Peripherals

All peripherals need two clock signals:

  • The generic clock from GCLK (asynchronous) in green
  • The interface clock from MCLK (synchronous) in light blue

There is no specific order in the configuration between asynchronous and synchronous clock.
The picture below shows the configuration of the SERCOM0, but the same process can be applied for any other peripherals such as ADC, TC, etc.
The GCLK multiplexer ID number (#11 for the GCLK_SERCOM0_CORE ) can be found in the data sheet. (Refer to the table in the GCLK_PCHCTRLm register description).

Configuring a Peripheral can be realized in four steps:

  • Enable the source clock (OSCCTRL / OSC32KCTRL)
  • Enable and configure a Generic Clock Generator (GCLK)
  • Enable and configure the appropriate Generic Clock Multiplexer to adress the targeted peripheral (GCLK)
  • Unmask the peripheral interface clock (MCLK)

You can find an example on how to configure the TC peripheral below.
Also, you will find several code snippet examples.

Asynchronous or Synchronous clock path

As the CPU and the peripherals can be clocked from different clock sources, possibly with widely different clock speeds, some peripheral accesses by the CPU need to be synchronized between the different clock domains.


The interest in having such flexible architecture is mainly for power consumption optimization:
In low power mode, peripherals can remain clocked by an external clock signal while all system clocks are OFF.


Write-Synchronized registers:

All peripherals are composed of one digital bus interface connected to the APB or AHB bus and running from a corresponding clock in the Main Clock domain, and one peripheral core running from the peripheral Generic Clock (GCLK).

Communication between these clock domains must be synchronized. This mechanism is implemented in
hardware, so the synchronization process takes place even if the peripheral generic clock is running from
the same clock source and on the same frequency as the bus interface.

All registers in the bus interface are accessible without synchronization.
All registers in the peripheral core are synchronized when written.
Some registers in the peripheral core are synchronized when read.

Each individual register description will have the properties "Read-Synchronized" and/or "Write-Synchronized" if a register needs to be synchronized. Each register that requires synchronization has its individual synchronizer and its individual synchronization status bit in the Synchronization Busy (SYNCBUSY) register.

Note: For registers requiring both read/write-synchronization, the corresponding bit in SYNCBUSY is shared.

Write-Synchronization is triggered by writing to a register in the peripheral clock domain (GCLK). The respective bit in the SYNCBUSY register will be set when the write-synchronization starts and cleared when the write-synchronization is complete. When write-synchronization is ongoing for a register, any subsequent write attempts to this register will be discarded, and an error will be reported through the Peripheral Access Controller (PAC).

In order to check if synchronization is complete, the user can either poll the relevant bits in SYNCBUSY or use the Synchronisation Ready interrupt (if available). The Synchronization Ready interrupt flag will be set when all ongoing synchronizations are complete (i.e., when all bits in SYNCBUSY are "0").

Code snippet: how to Configure a Write-Synchronized Peripheral (Timer Counter (TC))

On Demand Clock Request and Run in StandBy Capability

On Demand Clock Request

The ONDEMAND bit is related to clock sources only (i.e., each clock source can run in on-demand mode). Setting this bit allows the clock source to be switched off automatically if no longer required by the peripheral or switched on if a peripheral requests it again.

The clock source is in a stopped state unless a peripheral is requesting the clock source. Clock requests propagate from the peripheral, via the GCLK, to the clock source. If one or more peripheral is using a clock source, the clock source will be started/kept running. As soon as the clock source is no longer needed and no peripheral has an active request, the clock source will be stopped until requested again.

The clock request can reach the clock source only if the peripheral, the generic clock and the clock from the Generic Clock Generator in-between are enabled. The time taken between a clock request being asserted and the clock source being ready, depends on the clock source startup time, clock source frequency and the divider used in the Generic Clock Generator.

Timing Formulas and more details are provided in the product data sheet.

In Low Power mode, the clock request mechanism is still working if the modules are configured to run in Standby mode (RUNSTDBY bit set). Do not forget to consider the clock activation delays when using this feature.

Run in Standby Capability

The Run in Standby (RUNSTDBY) bit is related to Clock sources AND Peripherals (except EIC, TRAM, NVMCTRL, PORT, and PTC). This bit enables the capability for a clock source or a peripheral to run in STANDBY Low power mode without CPU interventions.


Here is a table that summarizes the device behaviors according to the ONDEMAND & RUNSTDBY bit configurations:



Once combined with the ON DEMAND Bit, a peripheral is then able to request its own clock asynchronously to run in STANDBY Low Power mode, performing tasks without waking up the CPU from STANDBY mode. This is called SleepWalking. In this SleepWalking mode, the CPU sleeps until a relevant event occurs (interrupts). This feature directly induced by the SAM L10/L11 architecture is vital to reach very low power consumption.

You will find several code snippet examples for each peripheral listed in the peripherals section.

Related Sections

Low Power Techniques
Learn more >
SAM L10 L11 family
Learn more >
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