SAM L10/L11 Internal SRAM

Internal SRAM Description

SAM L10/L11 devices embed 4 kB, 8 kB, or 16 kB of internal SRAM mapped at address 0x20000000.

SRAM retention is guaranteed for Watchog, External and System Reset resets. However, the first two 2 kB of SRAM are reset by the Boot ROM.

Internal SRAM Characteristics:

  • Up to 16 kB SRAM
  • Privileged access for Core, DSU, DMA
  • Four levels Quality of Service (QoS) for concurrent accesses
    • DISABLE
    • LOW
    • MEDIUM
    • HIGH
  • Divided in sub-blocks of 4 kB (to optimize power consumption)
    • SRAM can be partially retained in STANDBY by using the SRAM Power Switch in the Power Manager (PM)
  • Support Secure/Non-Secure regions' configuration for Arm® TrustZone® technology (SAM L11 only)
saml10-internal-sram.png

  Return to Top

© 2024 Microchip Technology, Inc.
Notice: ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries.
Information contained on this site regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.