SAM L10 MCU Overview

Microchip's SAM L10 MCU is the industry’s first and lowest power consuming Arm® Cortex®-M23 MCU (less than 25 µA/MHz in Active mode and less than 100 nA in Sleep mode). It features an enhanced Peripheral Touch Controller, ISO7816 Smart Card Interface, Event System, SleepWalking peripherals and advanced analog. The SAM L10 comes in 24- and 32-pin package options and is targeted for use in IoT and security, low power, capacitive touch, and general-purpose embedded control applications.



Operating Conditions:

  • Voltage range: 1.62 V to 3.63 V
  • Temperature range: -40 ºC to +125 ºC
  • Operational Frequency: DC to 32 MHz


  • Arm Cortex-M23
  • 32 MHz (2.64 CoreMark/MHz and up to 31 DMIPS)
  • Single-cycle hardware multiplier
  • Hardware divider
  • Nested Vector Interrupt Controller (NVIC)
  • Memory Protection Unit (MPU)


  • 64/32/16 KB Flash
  • 16/8/4 KB SRAM
  • 2 KB Data Flash Write-While-Read (WWR) section for non-volatile data storage
  • 256 bytes TrustRAM (TRAM) with physical protection features

Clock Management

  • Flexible clock distribution optimized for low power
  • 32.768 kHz crystal oscillator
  • 32.768 kHz ultra-low-power internal RC oscillator
  • 0.4 to 32 MHz crystal oscillator
  • One frequency meter
  • 16/12/8/4 MHz low-power internal RC oscillator
  • Ultra-low-power digital Frequency-Locked Loop (DFLLULP)
  • 48-96 MHz fractional digital Phase-Locked Loop (FDPLL96M)

Low Power and Power Management

  • Active, Idle, Standby with partial or full SRAM retention and off Sleep modes
    • Active mode (< 25 μA/MHz)
    • Idle mode (< 10 μA/MHz) with 1.5 μs wake-up time
    • Standby with Full SRAM Retention (0.5 μA) with 5.3 μs wake-up time
    • Off mode (< 100 nA)
  • Static and dynamic power gating architecture
  • SleepWalking peripherals
  • Two performance levels
  • Embedded Buck/LDO regulator with on-the-fly selection

Safety & Security

  • Up to four tamper pins for static and dynamic intrusion detection
  • Data Flash
    • Optimized for secrets storage
    • Address and Data Scrambling with a user-defined key (optional)
    • Rapid Tamper erase on scrambling key and on one user-defined row
    • Silent access for side-channel attack resistance
  • TRAM
    • Address and Data scrambling with a user-defined key
    • Chip-level tamper detection on physical RAM to resist micro probing attacks
    • Rapid Tamper Erase on scrambling key and RAM data
    • Silent access for side-channel attack resistance
    • Data remanence prevention
  • Peripherals
    • One True Random Generator (TRNG)
    • AES-128, SHA-256, and GCM cryptography accelerators (optional)
    • Secure pin multiplexing to isolate on dedicated I/O pins a secured communication with external devices from the non-secure application (optional)
  • TrustZone® for flexible hardware isolation of memories and peripherals (optional)
    • Up to six regions for the Flash
    • Up to two regions for the Data Flash
    • Up to two regions for the SRAM
    • Individual security attribution for each peripheral, I/O, external interrupt line, and Event System Channel
  • Secure Boot with SHA-based authentication (optional)
  • Up to three debug access levels
  • Up to three chip erase commands to erase part of or the entire embedded memories
  • Unique 128-bit serial number

Advanced Analog and Touch

  • One 12-bit 1 Msps Analog-to-Digital Converter (ADC) with up to 10 channels
  • Two Analog Comparators (AC) with window compare function
  • One 10-bit 350 kSPS Digital-to-Analog Converter (DAC) with external and internal outputs
  • Three Operational Amplifiers (OPAMP)
  • One enhanced Peripheral Touch Controller (PTC):
    • Up to 20 self-capacitance channels
    • Up to 100 (10 x 10) mutual-capacitance channels
    • Low-power, high-sensitivity, environmentally robust capacitive touch buttons, sliders, and wheels
    • Hardware noise filtering and noise signal desynchronization for high conducted immunity
    • Driven Shield Plus for better noise immunity and moisture tolerance
    • Parallel Acquisition through Polarity control
    • Supports wake-up on touch from Standby Sleep mode

Communication Interfaces

  • Up to three Serial Communication Interfaces (SERCOM) that can operate as:
    • Universal Synchronous Asynchronous Receiver Transmitter (USART) with full-duplex and single-wire half-duplex configuration
    • I²C up to 3.4 Mbit/s (High-Speed mode) on one instance and up to 1 Mbit/s (Fast-mode Plus) on the second instance
    • Serial Peripheral Interface (SPI)
    • ISO7816 on one instance
    • RS-485 on one instance
    • LIN Slave on one instance
    • Timers/Output Compare/Input Capture
  • Three 16-bit Timers/Counters (TC), each configurable as:
    • One 16-bit TC with two compare/capture channels
    • One 8-bit TC with two compare/capture channels
    • One 32-bit TC with two compare/capture channels, by using two TCs
  • 32-bit Real-Time Counter (RTC) with clock/calendar functions
  • Watchdog Timer (WDT) with Window mode
    • Input/Output (I/O)
  • Up to 25 programmable I/O lines
  • Eight External Interrupts (EIC)
  • One Non-Maskable Interrupt (NMI)
  • One Configurable Custom Logic (CCL) that supports:
    • Combinatorial logic functions, such as AND, NAND, OR, and NOR
    • Sequential logic functions, such as Flip-Flop and Latches
    • Qualification and Class-B Support
  • AEC-Q100 REVH: Grade 1 (40 ºC to +125 ºC) planned
  • Class-B safety library, IEC 60730 (future)
    • Debugger Development Support
  • Two-pin Serial Wire Debug (SWD) programming and debugging interface

Development Support:

  • Atmel Studio 7 IDE
  • Atmel START Software Framework



Block Diagram

ATSAML10E16A Block Diagram

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Explore the SAM L10 MCU:

Processor & Architecture
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Clock System Overview
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