SAM L10/L11 Oscillators Controller (OSCCTRL)

Oscillators Controller (OSCCTRL)


The OSCCTRL provides a user interface to the XOSC, OSC16M, DFLLULP and FDPLL96M. It is possible to enable, disable, calibrate, and monitor the OSCCTRL oscillators through the interface registers. All oscillators statuses are collected in the Status (STATUS) register. They can additionally trigger interrupts upon status changes via the INTENSET, INTENCLR, and INTFLAG registers.

I/O lines are configured by OSCCTRL when XOSC is enabled and need no user configuration.

The OSCCTRL can continue to operate in any Sleep mode where the selected source clock is running. The OSCCTRL interrupts can be used to wake up the device from Sleep modes. The events can trigger other operations in the system without exiting Sleep modes.


  • 0.4-32 MHz Crystal Oscillator (XOSC)
    • Tunable gain control
    • Programmable start-up time
    • Crystal or external input clock on XIN I/O
    • Clock failure detection with safe clock switch
    • Clock failure event output
  • 16 MHz Internal Oscillator (OSC16M)
    • Fast startup
    • 4/8/12/16 MHz output frequencies available
  • Ultra Low-Power Digital Frequency Locked Loop (DFLLULP)
    • Operates as a frequency multiplier against a known frequency in Closed Loop mode
    • Optional frequency dithering
  • Fractional Digital Phase Locked Loop (FDPLL96M)
    • 32 MHz to 96 MHz output frequency
    • 32 kHz to 2 MHz reference clock
    • A selection of sources for the reference clock
    • Adjustable proportional integral controller
    • Fractional part used to achieve 1/16th of reference clock step

Block Diagram


The OSCCTRL gathers controls for all device oscillators and provides clock sources to the Generic Clock Generator Controller (GCLK).
The available clock sources are XOSC, OSC16M, DFLLULP, and FDPLL96M.

The 0.4-32 MHz crystal must be connected between the XIN and XOUT pins, along with any required load capacitors.

The OSCCTRL bus clock (CLK_OSCCTRL_APB) can be enabled and disabled in the Main Clock Controller (MCLK). The control logic uses the oscillator output, which is also asynchronous to the user interface clock (CLK_OSCCTRL_APB). Due to this, writes to certain registers will require synchronization between the clock domains.

Principle of Operation

XOSC, OSC16M, and FDPLL96M are configured via OSCCTRL registers. Through this interface, the oscillators are enabled, disabled, or have their calibration values updated. The Status register gathers different status signals coming from the oscillators controlled by the OSCCTRL. The status signals can be used to generate system interrupts, and in some cases wake the system from Sleep mode.

Refer to the Clock System Section and to Generic Clock Generator Controller (GCLK) to get more details.

Refer to the "OSCCTRL – Oscillators Controller" chapter from the product data sheet to get more details.

Code Examples

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