SAM L10/L11 Performance Levels

Performance Levels Overview

The SAM L10/L11 device architecture provides software switchable Performance Levels (PLx), allowing flexible efficiency versus application scenarios. PLx offer the best flexibility between performance and power consumption.

If the application requires high performance and high frequency, the highest Performance Level (PL2) is the best choice.
If the application requires power efficiency and minimum power consumption, the lowest Performance Level (PL0) is the best choice.

It is the application's responsibility to configure the appropriate PLx depending on the application activity level required.

The PLx functionality consists of adjusting the regulator output voltage to reduce power consumption. You can select on the fly the performance level configuration which best suits the application. Each of the PLx has a maximum operating frequency and a corresponding maximum consumption in μA/MHz.

Refer to the "Electrical Characteristics" chapters in the device data sheet for details on energy consumption and maximum operating frequency.

The SAM L10/L11 support two different performance levels: PL0 and PL2.

The default PLx after reset is PL0. This aims for the lowest power consumption by limiting logic speeds and CPU frequency. As a consequence, some peripherals and clock sources will work with limited capabilities.

Full device functionality and performance will be ensured with PL2 mode.

Related Peripherals

The related peripheral to control the Voltage Regulator is the Power Manager.

Performance Level Selection

The Performance Level Controller, which is a part of the device Power Manager (PM), allows you to optimize your application either for low power consumption or high performance. The application can change the performance level on the fly by configuring the Performance Level Select bit in the Performance Level Configuration register (PLCFG.PLSEL). The Performance Level Disable bit in the Performance Level Configuration register (PLCFG.PLDIS) can be used to freeze the performance level to PL0. This disables the performance level hardware mechanism in order to reduce both the power consumption and the wake-up startup time from Standby Sleep mode.

IMPORTANT NOTE:

When changing to a lower performance level, the bus frequency must be reduced before writing PLCFG.PLSEL in order to avoid exceeding the limit of the target performance level.
When changing to a higher performance level, the bus frequency can be increased only after the Performance Level Ready flag in the Interrupt Flag status and Clear (INTFLAG.PLRDY) bit is set to '1', indicating that the performance level transition is complete.
The bit PLCFG.PLDIS must be changed only when the current performance level is PL0.