SERCOM Serial Peripheral Interface (SPI)

Overview

The SPI is one of the available modes in the Serial Communication Interface (SERCOM). The SPI uses the SERCOM transmitter and receiver configured as shown in the block diagram below. Each side, Master and Slave, depicts a separate SPI containing a shift register, a transmit buffer and a two-level or four-level receive buffer. In addition, the SPI Master uses the SERCOM baud-rate generator, while the SPI Slave can use the SERCOM address match logic.

Features

SERCOM SPI includes the following features:

• Full-duplex, four-wire interface (MISO, MOSI, SCK, /SS)
• One-level transmit buffer, two-level or four-level receive buffer
• Supports all four SPI modes of operation
• Single data direction operation allows alternate function on MISO or MOSI pin
• Select-able LSB- or MSB-first data transfer
• Can be used with DMA
• Master operation:
  • Serial clock speed, fSCK=1/tSCK (For tSCK and tSSCK values, refer to SPI Timing Characteristics.)
  • 8-bit clock generator
  • Hardware controlled SS

Block Diagram

Principle of Operation

In order to use the SERCOM’s I/O lines, the I/O pins must be configured using the IO Pin Controller (PORT). When the SERCOM is configured for SPI operation, the SERCOM controls the direction and value of the I/O pins. Both PORT control bits, PINCFGn.PULLEN and PINCFGn.DRVSTR, are still effective. If the receiver is disabled, the data input pin can be used for other purposes. In SPI Master mode, the Slave Select line (SS) is hardware-controlled when the Master Slave Select Enable bit in the Control B register (CTRLB.MSSEN) is '1'.

The combined configuration of PORT, the Data In Pinout and the Data Out Pinout bit groups in the Control A register, CTRLA.DIPO and CTRLA.DOPO, define the physical position of the SPI signals.

The SERCOM bus clock (CLK_SERCOMx_APB) can be enabled and disabled in the Main Clock Controller. A generic clock (GCLK_SERCOMx_CORE) is required to clock the SPI. This clock must be configured and enabled in the Generic Clock Controller before using the SPI. This generic clock is asynchronous to the bus clock (CLK_SERCOMx_APB), therefore, writes to certain registers will require synchronization to the clock domains.

The DMA request lines are connected to the DMA Controller (DMAC). In order to use DMA requests with this peripheral, the DMAC must be configured first. The interrupt request line is connected to the Interrupt Controller. In order to use interrupt requests of this peripheral, the Nested Vectored Interrupt Controller (NVIC) must be configured first.

The SPI is a high-speed synchronous data transfer interface. It allows high-speed communication between the device and peripheral devices. The SPI can operate as Master or Slave. As Master, the SPI initiates and controls all data transactions. The SPI is single-buffered for transmitting and double-buffered for receiving. When transmitting data, the Data register can be loaded with the next character to be transmitted during the current transmission. When receiving, the data is transferred to the two-level or four-level receive buffer, and the receiver is ready for a new character. The SPI transaction format is shown below. Each transaction can contain one or more characters. The character size is configurable and can be either eight or nine bits.

The SPI Master must pull the Slave Select line (SS) of the desired Slave low to initiate a transaction. The Master and Slave prepare data to send via their respective shift registers, and the Master generates the serial clock on the SCK line. Data are always shifted from Master to Slave on the Master Output Slave Input line (MOSI); data is shifted from Slave to Master on the Master Input Slave Output line (MISO). Each time a character is shifted out from the Master, a character will be shifted out from the Slave simultaneously. To signal the end of a transaction, the Master will pull the SS line high.

Code Example