Configuring the Configurable Custom Logic (CCL) peripheral requires the Look-Up Table (LUT) controls within the CCL to be set up through a series of registers.

Enabling, Disabling, and Resetting

The CCL is enabled by writing a '1' to the Enable bit in the Control register CTRL.ENABLE. The CCL is disabled by writing a '0' to CTRL.ENABLE.

Each LUT is enabled by writing a '1' to the Enable bit in the LUT Control x register LUTCTRLx.ENABLE. Each LUT is disabled by writing a '0' to LUTCTRLx.ENABLE.

The CCL is reset by writing a '1' to the Software Reset bit in the Control register CTRL.SWRST. All registers in the CCL will be reset to their initial state, and the CCL will be disabled.

Initialization

The following bits are enable-protected, meaning that they can only be written when the corresponding even LUT is disabled LUTCTRL2x.ENABLE=0:

• Sequential Selection in Sequential Control x register SEQCTRLx.SEQSEL

The following registers are enable-protected, meaning that they can only be written when the corresponding LUT is disabled LUTCTRLx.ENABLE=0:

• LUT Control x register, except ENABLE bit LUTCTRLx

Enable-protected bits in the LUTCTRLx registers can be written at the same time as LUTCTRLx.ENABLE is written to '1', but not at the same time as LUTCTRLx.ENABLE is written to '0'.

LUT Control

The LUT controls within the CCL have multiple input selections that are multiplexed through a combination of logic blocks.

The control for the combinatorial ends up being a single 8-bit field with values from 1 to 255 (0 is not valid). It is structured like this:

LUT Inputs

Possibilities for the three input lines IN[2:0] are controlled by the LUTCTRL.x register.

Masked Input

Option 0x0, Masked Input, is just grounding that input:

Feedback Input

Option 0x1, Feedback Input source, represents the output of the sequential logic block (described later) made available to both the LUTs that control that sequential block. This is pictured below.

Linked Input

Option 0x2, Linked LUT Input Source, is the output of the next highest numbered LUT:

Event System Input

Option 0x3 is from the Event System.
The CCLs capability can be greatly enhanced by interacting with the Event System.
The CCL can be both an event user and event generator. Note that as an event user (that is, events are coming into the LUTs), rising edges are always edge detected and turned into a pulse whose width is set by the asynchronous clock chosen for the CCL. This picture from the datasheet is the most accurate in that the edge detector is shown as always present and before the input to the LUT.

Being an event generator (output of LUTs feeding the Event System) is what allows the CCL to:

• Trigger actions in many of the peripherals
• Interact with the core through the generation of interrupts or setting flags
• Route a signal to any GPIO pin (the direct output of the CCL is limited to just a handful of pins, often with only one option for a particular LUT)

LUT AC Inputs

Option 0x4, AC Input source

LUT IO Pin Inputs

Option 0x5, Input Pin source for connecting to an I/O pin.

LUT TC Inputs

Option 0x6 and 0x7, are TC Input sources from the Timer Counter peripheral.

LUT TCC Inputs

Option 0x8, TC Input source is from the Timer Counter and Control peripheral.

LUT SERCOM Inputs

Option 0x9, TC Input source is from the Serial Communication Peripherals.

Other LUT Input Information

1. I/O pins as inputs/outputs to LUT: A given input pin is restricted to a particular LUT input/output. In general, one should place the pins needed first and then work other signals around those. Alternatively, board routing may need to be altered to accommodate restrictions imposed by item 4 above
2. At any one time, any LUT can accept only one event system channel, i.e. a LUT cannot directly bring in multiple events. This restriction is imposed by the Event User Multiplexer (MUX). Further, only asynchronous events may be used. Set up is fairly involved so we have examples using events both as inputs and outputs of the CCL
3. LUTs can be linked but they must be contiguous in number. Specifically, the subsequent LUT output is used as the LUT input (e.g., LUT2 is the input for LUT1)
4. When LUT outputs are synchronized/filtered there will be a variable 2-5 CCL GCLK (asynchronous clock driving the CCL) delay.

LUT Outputs

The output of the LUT can be passed on, synchronized to other channels within the CCL, or filtered to remove spikes associated with asynchronous inputs.

Separately, outputs of the synchronizer/filter block can be edge detected:

After the optional synchronizer/filter and edge detector blocks is Optional Sequential Logic, the options are:

Detailed drawings are below. Note that any clock to these flip flops is supplied by the asynchronous clock that the user selects for the CCL block.