Configurable Custom Logic (CCL)

The Configurable Custom Logic (CCL) peripheral provides a direct connection to a combination of device pins, analog comparator outputs, Timer/Counter's (TC), Timer/Counters for Control (TCC), Serial Communications (SERCOM), and Event System. Because the CCLs connect to both inputs and outputs of the Event System, most peripherals not listed above can still interact with the CCLs by being brought in, or driven through Event System Channels (i.e., outputs of the CCL can indirectly trigger events, interrupts or flags for the core, and actions in ADCs, DACs, timers, and SERCOMs).

What is the CCL?

The CCL is made up of multiple channels. Each channel consists of Combinatorial logic, followed by optional synchronization, filtering and/or edge detection, and optional sequential logic.


Combinatorial Logic is implemented as a three input Look Up Table (LUT). This allows for not just straightforward logic gates but custom logic as well. A note on terminology; while the term CCL refers to the collection of logic channels, the terms CCL0, CCL 1, CCL 2, and CCL 3 are used synonymously with the terms LUT 0, LUT 1, LUT 2, and LUT 3, respectively throughout the datasheet, and device headers, and any references on this site.

Each LUT consists of three inputs, a truth table, filter/synchronizer, and edge detector. Each LUT can generate an output as a user-programmable logic expression from any of the inputs. A LUT can be connected to another independent, adjacent LUT (LUT0/LUT1, LUT2/LUT3, etc.) enabling complex waveform generation.

CCL Strong points

  1. Use of a three-input Look Up Table (LUT) allows for custom logic.
  2. By enabling Edge Detection, rising/falling edges coming into the LUTs can be turned into pulses of 1 clock duration.
  3. Since events can be inputs to the LUTs, most peripherals can feed the LUTs, albeit indirectly.
  4. Each LUT can bring in a different event.
  5. The output of each additional LUT can be synchronized to each other and optionally filtered to remove spikes.
  6. Signals within the CCL can be synchronized to whatever asynchronous clock you choose to run the CCL with.
  7. Since the LUT outputs can be routed to the Event System, the CCL can generate all the triggers that are available to the Event System (actions in peripherals, flags or interrupts to the core, control of GPIO).

Design Considerations when using the CCL Peripheral block

  1. CCLs can only drive I/O or feed the Event System. Note that the Event System can then provide the flag setting and interrupt triggers for CCL outputs.
  2. As the datasheet indicates, LUT control fields are enable-protected: changes to the TRUTH or LUTSEL fields can only be made if the CCL and the respective LUT is disabled. Attempts to update these fields on an enabled LUT/CCL are ignored.
  3. The LUTs are not identical as to what peripheral signals they can bring in.
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