The 10/12-bit Analog-to-Digital Conversion (ADC) module in the PIC32 MCUs has up to 48 channels with the following features:
- External voltage reference input pins
- Sample-and-Hold (S&H) circuits
- Digital comparators
- Oversampling filters
- Flexible and independent ADC trigger sources
- 32-bit conversion result registers
- Operation during CPU sleep and idle modes
The MPLAB® Harmony PLIB library provides a low-level abstraction of the ADC module on Microchip microcontrollers with a convenient C language interface. This topic describes how that abstraction is modeled in software and introduces the library's interface.
Hardware Abstraction Model
The ADC module accepts an analog signal at any one instance and converts it to a corresponding 10-bit or 12-bit digital value. It can accommodate a number of analog inputs and separate reference inputs; the actual number available on a particular device depends on the package size.
A combination of input multiplexers can select the signal to be converted from multiple analog input pins. The entire multiplexer path includes provision for differential analog input, although the number of negative input pins is limited, and the signal difference must remain positive (i.e. unipolar).
An internal Sample and Hold (S&H) circuit acquires a sample of an input signal then holds that value constant during the conversion process. The purpose of the S&H circuitry is to take a snapshot of the sensor signal and hold the value. The sampled voltage is held and converted to a digital value, which strictly speaking, represents the ratio of that input voltage to a reference voltage. Configuration choices can allow connection of an external reference or use of the device power and ground (AVDD and AVSS).
The heart of the ADC is the conversion logic that converts the analog signal value into its equivalent discrete representation. Conversions can be started individually by program control, continuously free-running, or triggered by selected hardware events. A single channel may be repeatedly converted, alternate conversions may be performed on two channels, or any or all of the channels may be sequentially scanned and converted according to a user-defined bit map.
The resulting conversion output is a 10-bit or 12-bit digital number that can be signed or unsigned, left- or right-justified in a 16-bit word.
ADC Timing Details
Sample time is the time that the ADC module’s S&H circuit is connected to the analog input pin. The sample time may be started and ended automatically by the ADC’s hardware or under direct program control. There is a minimum sample time to ensure that the S&H circuit will provide sufficient accuracy for the analog-to-digital conversion.
Conversion time is the time required for the ADC to convert the voltage held by the S&H circuit. The conversion trigger ends the sampling time and Framework Help Peripheral Libraries Help ADC Peripheral Library begins an analog-to-digital conversion or a repeating sequence. The conversion trigger sources can be taken from a variety of hardware sources or can be controlled directly in software. Once the conversion is complete, the S&H circuit can be reconnected to the input pin and a CPU interrupt may be generated. The sum of the sample time and the analog-to-digital conversion time provides the total ADC sequence time. The following figure shows the basic conversion sequence and the relationship between intervals.
ADC Sample/Convert Sequence
The conversion trigger sources can be taken from a variety of hardware sources, or can be controlled directly by software. One of the conversion trigger options is an auto-conversion, which uses a counter and the ADC clock to set the time between auto-conversions. The Auto-Sample mode and auto-conversion trigger can be used together to provide continuous automatic conversions without software intervention.
A sample/convert sequence that uses multiple S&H channels can be simultaneously sampled or sequentially sampled. Simultaneously sampling multiple signals ensures that the snapshot of the analog inputs occurs at precisely the same time for all inputs. Sequential sampling takes a snapshot of each analog input just before conversion starts on that input. The sampling of multiple inputs is not correlated.
On some devices, S&H circuits have analog multiplexers on both their non-inverting and inverting inputs to select which analog input(s) are sampled. The ADC of some devices incorporate two independent sets of input multiplexers (MUX A and MUX B), which allow users to choose the analog channels that are to be sampled. Functionally, MUX A and MUX B are very similar to each other. Both multiplexers allow any of the analog input channels to be selected for individual sampling and allow selection of a negative reference source for differential signals. In addition, MUX A can be configured for sequential analog channel scanning. By default the ADC only samples and converts the inputs selected by MUX A. There is also the possibility of alternating between two sets of inputs selected by MUX A and MUX B during successive samples.
MUX Abstraction Model
When using MUX A to select analog inputs, the ADC module has the ability to scan multiple analog channels sequentially.
The ADC module provides a flexible mechanism to select analog inputs for conversion:
- Fixed input selection
- Alternate input selection
- Channel scanning
Fixed Input Selection
This is achieved through one or more of the S&H channels available in the device. The S&H channels are connected to the analog input pins through the analog multiplexer.
In an Alternate Input Selection mode, the ADC completes one sweep using the MUX A selection, then another sweep using the MUX B selection, and then another sweep using the MUX A selection, and so on.
Alternate Input Selection in 2-Channel Sequential Sampling Configuration
On some devices, the ADC module supports the Channel Scan mode using S&H Channel 0 (CH0). The number of inputs scanned is software selectable. Any subset of the analog inputs from AN0 to AN31 (depending on the number of analog inputs present on a specific device) can be selected for conversion. The selected inputs are converted in ascending order. For example, if the input selection includes AN4, AN1, and AN3, the conversion sequence is AN1, AN3, and AN4.
Scan Four Analog Inputs Using CH0
Multi-Channel Sample Conversion
Multi-channel analog-to-digital converters typically convert each input channel sequentially using an input multiplexer. Simultaneously sampling multiple signals ensures that the snapshot of the analog inputs occurs at precisely the same time for all inputs. Certain applications require simultaneous sampling, especially when phase information exists between different channels. Sequential sampling takes a snapshot of each analog input just before conversion starts on that input. Certain ADC modules support simultaneous sampling using two S&H or four channels to sample the inputs at the same instance, and then perform the conversion for each channel sequentially.
Simultaneous and Sequential Sampling
Specifying Conversion Result Buffering for Devices with Direct Memory Access (DMA)
The ADC module contains a single-word, read-only, dual-port register, which stores the ADC conversion result. If more than one conversion result needs to be buffered before triggering an interrupt, DMA data transfers can be used. If DMA is supported and enabled, multiple conversion results can be automatically transferred from ADC internal buffer to a user-defined buffer in the DMA RAM area. Therefore the application can process several conversion results with minimal software overhead.
For more detail on the ADC module for a specific PIC32 device, please view the family reference manual chapter for that device, for example: