The MIPS32® Architecture defines the following Central Processing Unit (CPU) registers:
- Thirty-two 32-bit general purpose registers (GPRs)
- A special-purpose program counter (PC) that is affected only indirectly by certain instructions and is not architecturally visible
- One 64-bit Accumulator to hold the results of integer multiply, divide and multiply-accumulate operations (HI and LO)
General Purpose Registers
The MIPS® architecture has 32 general purpose CPU registers for your program use: $0 - $31.
Two, and only two, behave differently than the others: $0 & $31:
- $0 - Always returns zero, no matter what you store in it.
- $31 - Always used by the normal subroutine calling instruction (jal)
The remainder are identical and may be used in any instruction to hold data or addresses.
Although the hardware makes few rules about the use of registers, their practical use is governed by conventions that have been developed over time in order to facilitate code re-use.
With the conventional uses of the registers come the conventional set of names. The following table lists the conventional names of the registers with usages (from the MPLAB® XC32 Users Guide DS50001686G):
HI(x)/LO(x) Register Usage
- During a legacy multiply operation (mult), the HI and LO registers store the product of integer multiply. Special instructions are available to move HI/LO results to/from the register file (mfhi, mflo, mthi, mtlo)
- Multiply-Add (madd) and Multiply-Subtract (msub) produce a full-width product twice the width of the input operations and adds or subtracts the product from the concatenated value of HI and LO. The low half of the addition is loaded into LO and the high half is loaded into HI.
- Divide (div) produces a quotient that is loaded into LO and a remainder that is loaded into HI.