Depending on the device sub-family, PIC32MZ devices are a complex System-on-Chip (SoC), which are based on the microAptiv™ Microprocessor core or the M-Class M5150 Microprocessor core from Imagination Technologies Ltd.
The microAptiv™ Microprocessor core is a superset of the MIPS® M14KE™ and M14KEc™ Microprocessor cores. These cores are state of the art, 32-bit, low-power, RISC processor cores with the enhanced MIPS32® Release 2 Instruction Set Architecture (ISA).
The M5150 Microprocessor core is a superset of the microAptiv™ Microprocessor core. This 32-bit, low-power, RISC processor core uses the enhanced MIPS32® Release 5 Instruction Set Architecture (ISA).
The MIPS32® microAptiv™ MPU core implements Release 2 of the MIPS architecture in a 5-stage pipeline. It includes support for the microMIPS™ ISA, an Instruction Set Architecture with optimized MIPS32 16-bit and 32-bit instructions that provide a significant reduction in code size with a performance equivalent to MIPS32. The microAptiv™ MCU/MPU core is an enhancement of the M14Kc™, designed from the same microarchitecture, including the Microcontroller Application-Specific Extension (MCU™ ASE), enhanced interrupt handling, lower interrupt latency, nativeAMBA®-3 AHB-Lite Bus Interface Unit (BIU), with additional power saving, debug, and profiling features.
The following key features are available on PIC32 MCUs based on this core:
- microMIPS™ variable-length instruction mode for compact code
- Vectored interrupt controller with up to 256 interrupt sources
- Atomic bit manipulations on peripheral registers (Single cycle)
- High-speed Microchip ICD port with hardware-based non-intrusive data monitoring and application data streaming functions
- EJTAG debug port allows extensive third party debug, programming, and test tools support
- Instruction controlled power management modes
- Five-stage pipeline instruction execution
- Internal-code protection to help protect intellectual property
- Arithmetic saturation and overflow handling support
- Zero-cycle overhead saturation and rounding operations
- Atomic read-modify-write memory-to-memory instructions
- MAC instructions with up to 4 accumulators
- Native fractional data type (Q15, Q31) with rounding support
- MIPS® Digital Signal Processing (DSP) Application-Specific Extension (ASE) Revision 2, which adds DSP capabilities with support for powerful data processing operations
- MIPS® MCU™ ASE, which adds enhancements in the areas of interrupt delivery and latency
- Multiply/Divide unit with a maximum issue rate of one 32 x 32 multiply per clock
The MIPS32® M5150 MPU core implements Release 5 of the MIPS architecture in a 5-stage pipeline. In addition to the features described for devices with the microAptiv™ core, the following key features are common to all PIC32 devices that are based on the M-Class M5150 Microprocessor core:
- Implements the latest MIPS Release 5 Architecture, which includes IP protection and reliability for industrial controllers, Internet of Things (IoT), wearables, wireless communications, automotive, and storage
- IEEE-754 Single/Double Precision Floating Point Unit (FPU)
ASE: An application-specific extension to the MIPS® architecture. These are optional extensions defined in add-ons to the MIPS32/MIPS64 base architecture. Refer to sections 50.14 and 50.15 in the PIC32MZ CPU Reference Manual for details on these ASEs
CPU Core Documentation:
The following documents are available from Imagination Technologies (user registration may be required):