Instruction Categories

CPU Instructions

MIPS32® Release 2 CPU instructions are organized into the following functional groups:

  • Load and Store: Used to load/store operands from memory to/from the GPR
  • Computational: Arithmetic, logic, and shift operations performed on integers represented in two's complement format
  • Jump and Branch: Instructions that modify the Program Counter (PC)
  • Miscellaneous: Exception handling, conditional move, cache prefetch, NOP
  • Coprocessor: Instructions that deal with the coprocessor units

Table 1 provides some example assembly language mnemonics for these categories:

cpu-instructions.png
Table 1

MIPS32 Release 2 CPU Instructions are fully documented in "MIPS® Architecture for Programmers Volume II-A: The MIPS32® Instruction Set Manual".

DSP Instructions

PIC32 MZ devices with microAptive or M5150 Core implement MIPS® DSP ASE Revision 2 instructions. They are classified into the following categories:

  • Arithmetic: Instructions that perform addition/subtraction of Q15/Q31 data
  • GPR-based Shift: Logical/arithmetic shift operations on DSP data
  • Multiply/Multiply-Accumulate: MAC operations on DSP data
  • Bit Manipulation: Specialized DSP bit operations
  • Compare-Pick: Element-wise comparisons
  • DSP Control Access: Instructions that access the DSP control register and accumulators
  • Indexed-Load: Indexed load sub-class
  • Branch: Specialized branch operation

Table 2 provides some example assembly language mnemonics for these categories:

dsp-instructions.png
Table 2

The DSP instruction set is nothing like the regular and orthogonal MIPS32 instruction set. It's a collection of special-case instructions, aimed at known hot-spots of important DSP applications.

MIPS DSP ASE Revision 2 DSP Instructions are fully documented in "MIPS® Architecture for Programmers Volume IV-e: The MIPS® DSP Module for the MIPS32® Architecture".

Floating Point Unit (FPU) Instructions

PIC32 MZ devices with the M5150 core implement MIPS64® Floating Point Unit instructions. They are classified into the following categories:

  • Data Transfer: Instructions for moving data to/from the FPU
  • Arithmetic: Operations on formatted data values
  • Conversion: These instructions perform conversions between floating point and fixed point data types
  • Formatted Move: Move formatted operand values among FPU general registers
  • Conditional Branch: PC-relative conditional branch instructions that test condition codes set by FPU compare instructions
  • Miscellaneous: Conditionally move one CPU general register to another, based on an FPU condition code

Table 3 provides some example assembly language mnemonics for these instruction categories:

fpu-instructions.png
Table 3

For more information on the FPU instruction set, please refer to chapter 12 (50.12) in the PIC32MZ family reference manual "Section 50. CPU for Devices with MIPS32® microAptiv™ and M-Class Cores".

Macro Instructions

Most MIPS assemblers will synthesize a set of macro (also called synthetic or pseudo) instructions intended to simplify the task of writing MIPS assembly language programs.

Every time a programmer specifies a macro instruction, the assembler replaces it with a set of actual MIPS instructions to accomplish a task.

For example, let us suppose a programmer used the load-immediate (li) macro instruction to load a 32-bit constant into a register:

The MIPS assembler would then insert the following two MIPS instructions to accomplish the task:

Some pseudo-instructions require a temporary register for intermediate calculations. Assemblers use register at for this purpose.

The mere existence of macro assembly instructions should be a warning sign to budding MIPS assembly language programmers - MIPS machine code might be rather dreary to write!

Visit the "MIPS architecture" article on Wikipedia for a list of commonly synthesized pseudo-instructions.

© 2024 Microchip Technology, Inc.
Notice: ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries.
Information contained on this site regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.