The Prefetch module is a performance enhancing module included in PIC32 devices with L1 CPU caches. When running at high-clock rates, Wait states must be inserted into Program Flash Memory (PFM) read transactions to meet the access time of the PFM. Wait states can be hidden to the core by prefetching and storing instructions in a temporary holding area that the CPU can access quickly. Although the data path to the CPU is 32-bits wide, the data path to the PFM is 128 bits wide. This wide data path provides the same bandwidth to the CPU as a 32-bit path running at four times the frequency.
The Prefetch module is designed to complement an L1 CPU cache rather than replace it. A single 128-bit (16-byte) line holds instructions or constant data from the PFM.
The PIC32MZ prefetch buffer contains 4 lines:
- 1 for instruction data
- 1 for constant data
- 2 for peripheral data
The Prefetch module uses the Wait states value from the PRECONPFMWS<2:0> bits to determine how long it must wait for a Flash access when it reads instructions or data from the PFM.
If the instructions or data already reside in a Prefetch module line, the Prefetch module returns the instruction or data in zero Wait states. For CPU instructions, if prefetch is enabled and the code is 100% linear, the Prefetch module will provide instructions back to the CPU with Wait states only on the first instruction of the Prefetch module line.
One Prefetch module line is allocated to CPU data and two lines are allocated to peripheral data. Which of these lines are enabled is determined by the PRECONPREFEN<1:0> bits.
Although the lines are enabled by type, the type is not used for matching. Therefore, the line allocated to CPU data and filled by CPU data can be read by a CPU instruction read or a non-CPU peripheral data read. A non-CPU peripheral could be DMA or any other peripheral that has read access to the PFM.
The Prefetch module does not support preloading, address masking, or line locking.
The following example code is for a PIC32MZ2048EFG100 device, whose oscillator configuration settings (not shown) are set for 200MHz SYSCLK. The initialization code simply enables the prefetch buffer (all lines), and sets the wait-states to 2 as per TABLE 37-13 in the data sheet, which is reproduced here: