Cache Coherency Defined

If the CPU were the only entity modifying memory, the cache would effectively be transparent to system operation, and we would never have cache coherency issues. In a PIC32 device, DMA and DMA enabled peripherals also modify memory. Therefore, any data that can be modified by both the CPU and DMA must be synchronized.

PIC32MZ cache coherency
Maintain consistent data between local memory for the CPU (cache) and local memory for DMA (main data memory)

If the CPU or DMA writes to memory, there is a chance the cache may no longer represent the contents of main memory. In this case, the cache will have “dirty” or “stale” data respectively. Before we show you how to manage this situation, let’s describe it in more detail.

Stale Cache

When DMA writes to a location that is already loaded into the cache, the cache no longer represents the contents of main data memory. When this occurs, the data in the cache is said to be “stale”. In this example, the CPU is not aware that “my_data” stored in cache is different from “my_data” in main memory.

This creates two problems.

  1. The CPU will work with stale data instead of the updated data.
  2. If the CPU modifies “my_data” in cache, it may write-back “my_data” to main memory, thus overwriting the data previously written by DMA.

Dirty Cache

In this example the CPU has brought “my_data” into cache and modified it without writing it back to main memory. This creates a dirty cache. If the DMA reads “my_data” it will be reading old (stale) data.

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