Cache Management Assembly Instructions

The PIC32 microAptiv core includes special instructions for managing the cache.


The CACHE instruction is primarily used at start-up to initialize the cache. To manage coherency, the CACHE instruction can be used to:

  • Invalidate a Cache Address Hit – Searches the cache for the specified address, and if a hit occurs, invalidates (evicts) the cache line. No write back is performed even if the cache line is dirty.
  • Write back a Cache Address Hit – Searches the cache for the specified address, and if a hit occurs and the line is dirty, writes the cache line to memory.
  • Fill Cache – Fills the instruction cache (I-Cache) with data from the specified address. For data cache (D-Cache) fills the PREF instruction is used.
  • Fetch and Lock – Fills the instruction or data cache with data from the specified address, and locks it in the cache. The data remains locked in the cache until it is invalidated with the cache instruction.


The PREFECT instruction (PREF) is provided to optimize D-Cache performance by allowing software to specify the optimum cache fill operation:

  • Fill a cache line for write operation: a cache line is reserved but no fill from memory is performed as memory will ultimately be written with new data.
  • Fill a cache line for a read operation: a cache line is reserved and filled with the contents of memory.
  • Streamed and Retained Options: allow the user to specify a cache hierarchy where streamed data will not evict retained data.
  • Write back and invalidate: allows the user to free a cache line, writing it back to memory if it is dirty. Sometimes referred to as ‘nudge’.

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