Peripheral Bus Clocks (PBCLKx)
PIC32MZ devices include more than one peripheral clock, allowing peripherals to run at different bus speeds, depending on the application. All peripheral clocks (except PBCLK1) also have individual enable/disable control.
Each peripheral clock is derived from the System Clock (SYSCLK) divided by the specific peripheral clock divisor setting (1 to 128). The maximum clock rate for most peripheral clocks is 100 MHz. The one exception to this is PBCLK7 which is 200 MHz (drives the core).
The peripheral bus frequency can be changed on the fly by writing a new value to the divisor bits. These bits are protected from accidental writes with an unlock sequence. A state machine ensures a stable transition from one clock frequency to another.
The following MPLAB® Harmony code provides several examples for controlling the peripheral clocks. These functions will perform all unlocking/locking and state machine control for you.
// PBCLK1=SYSCLK/2 PLIB_OSC_PBClockDivisorSet(OSC_ID_0, OSC_PERIPHERAL_BUS_1, 2); // enable PBCLK1 PLIB_OSC_PBOutputClockEnable(OSC_ID_0, OSC_PERIPHERAL_BUS_1); // disable PBCLK8 PLIB_OSC_PBOutputClockDisable(OSC_ID_0, OSC_PERIPHERAL_BUS_8);