PIC32MZ Oscillator - System Clock (SYSCLK)

System Clock (SYSCLK) Generation

sysclk.PNG

The System Clock provides the time base for the peripheral clocks, DMA, interrupts, and flash. SYSCLK is determined from one of the input clocks shown in the diagram (SPLL, POSC, FRCDIV, LPRC, BFRC, SOSC).

Note the PIC32MX uses SYSCLK to drive the core. This is NOT true for the PIC32MZ. The PIC32MZ core clock is provided by Peripheral Bus Clock #7 (PBCLK7).

You cannot choose to use the BFRC for SYSCLK. Only the hardware will use this when the fail-safe clock monitor (FSCM) detects a problem.

The default configuration for SYSCLK is programmable and can also be changed at run-time. See the code examples below.

// default system clock = FRCDIV
#pragma config FNOSC = FRCDIV
// default system clock = SPLL
#pragma config FNOSC = SPLL
...    
// run-time config SYSCLK = FRCDIV
PLIB_OSC_SysClockSelect(OSC_ID_0, OSC_FRC_BY_FRCDIV);
// run-time config SYSCLK = POSC with SPLL
PLIB_OSC_SysClockSelect(OSC_ID_0, OSC_PRIMARY_WITH_PLL);

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