PIC32MZ Configuration Registers

PIC32MZ Configuration Registers

A PIC32 family device includes several nonvolatile (programmable) Configuration Words that define device behavior. The device configuration features may vary according to PIC32 family variants; however, the following features are common to all PIC32 devices:

  • System Clock Oscillator mode and Phase-Locked Loop (PLL)
  • Secondary Oscillator (SOSC) enable/disable
  • Watchdog Timer (WDT) enable/disable and postscaler
  • Boot Flash and Program Flash write-protect regions
  • User ID
  • Debug mode

The PIC32 Configuration Words are located in Boot Flash memory and are programmed when the PIC32 Boot Flash region is programmed.

System clock oscillator and PLL bits provide a large selection of flexible clock source options and PLL prescalers/postscalers.

The SOSC bit enables or disables a low-power SOSC that can serve as a clock source for several peripherals, such as RTCC, Timer1 and CPU.

The WDT and postscaler bits allow the user to permanently disable or enable the WDT. When enabled, a postscaler can be selected to provide a wide range of WDT periods. A Windowed mode Watchdog feature is also available.

The Boot Flash and Program Flash write-protected bits provide write protection to all of Boot Flash memory and selected regions of Program Flash memory.

User ID bits are available for programming application-specific or product-specific identification information, such as product ID or serial numbers. Debug mode bits provide a selection of debugging modes and channels.

The following list shows all the device configuration registers for the PIC32MZ devices. The purpose of this list is to help you understand what these registers control. Please see the device data sheet (Special Features section) for details.

Note some of these configuration register have a related alternate configuration register. If an unrecoverable ECC error occurs when reading the Configuration Words, the Alternate Configuration Words are used to configure the device and Boot Flash memory. This configuration can be identical to the primary Configuration Words, or different to operate in another condition. To flag that an ECC error has occurred, the BCFGERR (RCON<27>) bit is set. If uncorrectable ECC errors are found in both primary and alternate words, the BCFGFAIL (RCON<26>) bit is set and the default configuration is used.

Device Configuration Register Bits found in register
Device Code Protect Register
Code Protect bit
Device Configuration Word0
EJTAG boot enable
Debug Mode CPU Access Permission bits
Flash Sleep Mode bit
Dynamic Flash ECC Configuration bits
Boot ISA Selection bit (MIPS32® or microMIPSTM)
Trace Enable bit
In-Circuit Emulator/Debugger Communication Channel Select bits
JTAG Enable bit
Background Debugger Enable bits
Device Configuration Word1
Deadman Timer enable bit
Deadman Timer Count Select bits
Watchdog Timer Window Size bits
Watchdog Timer Enable bit
Watchdog Timer Window Enable bit
Watchdog Timer Stop During Flash Programming bit
Watchdog Timer Postscale Select bits
Clock Switching and Monitoring Selection Configuration bits
Primary Oscillator Output pin (CLKO) Enable Configuration bit
Primary Oscillator Configuration bits
Internal External Switchover bit (for two-speed start-up)
Secondary Oscillator Enable bit
Deadman Timer Count Window Interval bits
Oscillator Selection bits
Device Configuration Word2
USB PLL Enable bit
USB PLL Input Frequency Select bit
Default System PLL Output Divisor bits
System PLL Feedback Divider bits
System PLL Input Clock Select bit
System PLL Divided Input Clock Frequency Range bits
PLL Input Divider bits
Device Configuration Word3
USB USBID Selection bit
Peripheral Pin Select Configuration bit (IOL1WAY)
Peripheral Module Disable Configuration bit
Permission Group Lock One Way Configuration bit
Ethernet I/O Pin Selection Configuration bit
Ethernet MII Enable Configuration bit
16-bit user-defined USERID bit readable via ICSP™ and JTAG
Configuration Control Register
DMA Read and DMA Write Arbitration Priority to SRAM bit
CPU Arbitration Priority to SRAM When Servicing an Interrupt bit
Input Capture Alternate Clock Selection bit
Output Compare Alternate Clock Selection bit
Peripheral Pin Select Lock bit
Peripheral Module Disable bit
Permission Group Lock bit
USB Suspend Sleep Enable bit
Flash ECC Configuration bits
JTAG Port Enable bit
Trace Output Enable bit
TDO Enable for 2-Wire JTAG
External Bus Interface Address Pin Configuration Register
EBI Pin Enable bit
EBI Address Pin Enable bits
External Bus Interface Control Pin Configuration Register
EBIRDY3 Inversion Control bit
EBIRDY2 Inversion Control bit
EBIRDY1 Inversion Control bit
EBIRDY3 Pin Enable bit
EBIRDY2 Pin Enable bit
EBIRDY1 Pin Enable bit
EBIRDYx Pin Sensitivity Control bit
EBIRP Pin Sensitivity Control bit
EBIWE Pin Enable bit
EBIOE Pin Enable bit
EBIBS1 Pin Enable bit
EBIBS0 Pin Enable bit
EBICS3 Pin Enable bit
EBICS2 Pin Enable bit
EBICS1 Pin Enable bit
EBICS0 Pin Enable bit
EBI Data Upper Byte Pin Enable bit
EBI Data Lower Byte Pin Enable bit
Permission Group Configuration Register
Crypto Engine Permission Group bits
Flash Control Permission Group bits
SQI Module Permission Group bits
Ethernet Module Permission Group bits
CAN2 Module Permission Group bits
CAN1 Module Permission Group bits
USB Module Permission Group bits
DMA Module Permission Group bits
DMA Module Permission Group bits
Device ID and Revision ID Register
Revision Identifier bits
Device ID bits
Device ADC Calibration Register
Calibration bits for the ADCs
Device Serial Number Register
Device Unique Serial Number bits

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