8-Bit AVR® General Purpose Registers

The AVR® register file structure is optimized for the AVR Enhanced Reduced Instruction Set Computer (RISC) instruction set. In order to achieve the required performance and flexibility, the following I/O schemes are supported by the register file:

  • One 8-bit output operand and one 8-bit result input.
  • Two 8-bit output operands and one 8-bit result input.
  • Two 8-bit output operands and one 16-bit result input.
  • One 16-bit output operand and one 16-bit result input.

AVR CPU General Purpose Working Registers

gpr.png

Most of the instructions operating on the register file have direct access to all registers and most of them are single cycle instructions. Each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user data space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y-, and Z-pointer registers can be set to index any register in the file.

The X-register, Y-register, and Z-register

Registers R26 through R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers (X, Y, and Z) are defined as described in the figure.

xyz.png
© 2024 Microchip Technology, Inc.
Notice: ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries.
Information contained on this site regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.