Analog to Digital Converter with Computation

The Analog-to-Digital Converter (ADC), with computation module (ADCC), in Microchip’s latest family of 8-bit MCUs, has a built-in computational feature that provides post-processing functions such as oversampling, averaging and low-pass filtering.

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The analog input channel sources are multiplexed into a single sample and hold circuit. The output of the sample and hold circuit is connected to the converter, which generates a binary representation of the analog input. When the ADC is operating with computational features, the conversion result will be passed onto the computational feature block for post-processing. The post-processing result is then evaluated using error calculation and threshold comparison.

Channel Selection Source

The ADCC Channel Selection register (ADPCH) determines which channel is connected to the sample and hold circuit. Channel selection sources are not limited to external analog input sources but can also be an output of a peripheral or and internal reference voltage.

Voltage Reference Source

The voltage reference sets the input voltage range of the ADC. It can be an external source from the VREF+/- pins, VDD, FVR, and VSS.

Conversion Clock Source

The conversion clock has multiple sources, either from the main oscillator, which is divided by multiples of two (i.e., 2, 4 or 128), or from the dedicated internal RC clock.

Auto-Conversion Trigger Source

The Auto-conversion Trigger allows the module to schedule acquisition and conversion sequences without software intervention. When a rising edge of the selected source occurs, the ADC Conversion Status bit (ADGO) bit is set. The sources for the auto-conversion trigger can be found on the device data sheet for the device you are using. In an application, these auto-conversion trigger sources can be used to set the sampling period of the ADC.

Operational Modes

Basic Mode

The Basic Mode of the ADCC mimics the legacy ADC operation. With the auto-trigger feature of the module, input sampling can be easily triggered in the software or by other peripherals and external sources. The result of the conversion can be compared to a threshold set point which may trigger the Analog-to-Digital Converter Interrupt Flag.

Accumulate Mode

In the Accumulate Mode, the digital representation of the analog input signal in the 10-bit ADRES register is accumulated to the 16-bit ADC Accumulator Register ADACC register. With each sample, ADC Conversion Counter Register (ADCNT) is incremented, indicating the number of samples accumulated. The accumulated value can be right shifted up to six times by changing the value of the ADC Accumulate Calculation Right Shift Select bits (ADCRS) of the ADC Control Register 2 (ADCON2) register. This means that the accumulated value is effectively divided by a factor of two (2ADCRS). The result of the shifted accumulated value is stored in the ADC Filter register (ADFLTR) register.

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Averaging Mode

The Average Mode is like an accumulate mode wherein the ADACC accumulates the data sample and the ADCNT increments with each sample, except that the number of samples being accumulated in this mode is up to the value set in the A/D Repeat Setting register (ADRPT). When the ADCNT is equal to ADRPT, the value stored in the ADC Filter register (ADFLTR) becomes the average value of the input signal. This mode can be used when a defined time interval is needed for each sample.

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Burst Average Mode

Like averaging mode, the Burst Average Mode averages the input signal except that the sampling is repeated quickly after a single trigger. This means that in a single conversion, all the data samples are accumulated up to the set ADRPT and when the ADCNT matches the set ADPRT value, the average value of the input signal is attained.

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Low-Pass Filter Mode

A Low-Pass Filter Mode passes signals with frequencies below its cutoff and attenuates frequencies above its cutoff. The ADCRS determines the low-pass filter order. Given the radian value in Table 4, the cutoff frequency (@ – 3dB gain) can be calculated using Equation 3.

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ADCC Output Actions

Threshold Comparison

The post-processing result of the ADCC module can be compared to the threshold value set in the ADC Error Calculation Mode Select bits (ADCALC) of the ADC Threshold register (ADCON3). The calculated result is stored in the ADC Calculation Error Register (ADERR), which can be compared to the selected upper or lower threshold. These two threshold values can be set by changing the ADC Upper Threshold (ADUTH) registers and the ADC Lower Threshold (ADLTH) registers. A result of true, based on the comparison, will trigger an interrupt.

Continuous Mode Retrigger

Enabling the Continuous mode allows an automatic sampling retrigger after the threshold has been tested. In this mode, the ADGO of the ADC Control Register 0 (ADCON0) remains set until the threshold conditions are met according to the selected Threshold Interrupt Mode Select bits (ADTMD) and the A/D Stop On Interrupt bit (ADSOI) of the ADC Threshold Register (ADCON3).

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