8-Bit CCP/ECCP Compare

Compare mode operates identically for both CCPx and ECCPx peripherals. Compare mode makes use of the 16-bit Timer1 peripheral. The 16-bit value of the combined 8-bit Compare register pair, CCPRxH:CCPRxL, is constantly compared against the 16-bit value of the Timer1 register pair TMR1H:TMR1L. When a match occurs, one of the following events can occur:

  • Toggle the CCPx output pin
  • Set the CCPx output pin
  • Clear the CCPx output pin
  • Generate a Special Event Trigger
  • Generate a Software Interrupt

The event action is based on the value of the CCPxM<3:0> control bits of the CCPxCON register. At the same time, the interrupt flag CCPxIF bit is set. All Compare modes can generate an interrupt (except for the Special Event Mode).

CCPxCON: CCPx Control Register

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
bit 7 bit 0

Timer1 (Compare Mode)

In Compare mode, Timer1 must be running in Timer mode or Synchronized Counter mode. The compare operation may not work in Asynchronous Counter mode. Reference the Timer1 module with Gate Control for more information on configuring Timer1.

Clocking Timer1 from the system clock (FOSC) should not be used in Compare mode. In order for Compare mode to recognize the trigger event, Timer1 must be clocked from the instruction clock (FOSC/4) or from an external clock source.

CCPx Pin Configuration (Compare Mode)

The software design must configure the CCPx pin as an output for the Compare mode by clearing the associated TRIS bit. On some newer devices, the CCPx pin function can be moved to alternative pins using the APFCON0 or APFCON1 registers while on others, it can be moved through the Peripheral Pin Select feature.


Special Event Trigger (Compare Mode)

If the A/D module is enabled, the Special Event Trigger output starts an A/D conversion. This mode can effectively provide a 16-bit programmable period register for Timer1. The CCPx module does not assert control of the CCPx pin in this mode.

When Special Event Trigger mode is chosen (CCPxM<3:0> = 1011), the CCPx module does the following:

  • Resets Timer1
  • Starts an A/D conversion if the ADC is enabled

The Special Event Trigger output of the CCP occurs immediately upon a match between the TMR1H:TMR1L register pair and the CCPRxH:CCPRxL register pair. The TMR1H:TMR1L register pair is not reset until the next rising edge of the Timer1 clock.

1: The Special Event Trigger from the CCP module does not set interrupt flag bit TMR1IF of the PIR1 register.

2: Remove the match condition by changing the contents of the CCPRxH:CCPRxL register pair between the clock edge that generates the Special Event Trigger and the clock edge that generates the Timer1 Reset. This will preclude the Reset from occurring.

Software Interrupt (Compare Mode)

All Compare modes can generate an interrupt (except the Special Event Mode). However, when the Generate Software Interrupt mode is chosen (CCPxM<3:0> = 1010), the CCPx module does not assert control of the CCPx pin.

To generate an interrupt the Global Interrupt Enable (GIE) bit and the CCPxIE bit in the corresponding Peripheral Interrupt Register must both be set. For more detail on the interrupt structure refer to the Interrupts Training Module.

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