8-Bit ECCP Enhanced Pulse Width Modulation

The Enhanced PWM (EPWM) function is similar to the standard PWM but with many added features. The EPWM is available on devices with the ECCP peripheral. The enhanced PWM mode generates a Pulse-Width Modulation (PWM) signal on up to four different output pins with up to 10 bits of resolution.

The enhanced PWM module can generate the following five PWM Output modes:

  • Single PWM
  • Half-Bridge PWM
  • Full-Bridge PWM, Forward Mode
  • Full-Bridge PWM, Reverse Mode
  • Single PWM with PWM Steering Mode

The period, duty cycle, and resolution for the EPWM are controlled by the following registers:

  • PRx registers
  • TxCON registers
  • CCPRxL registers
  • CCPxCON registers

The EPWM also has additional features such as Auto-shutdown, Auto-restart, Dead-band Delay and PWM Steering. Those are controlled by the following registers:

  • CCPxAS registers
  • PSTRxCON registers
  • PWMxCON registers

To select an Enhanced PWM Output mode, the PxM bits of the CCPxCON register must be configured appropriately. The PWM outputs are multiplexed with I/O pins and are designated PxA, PxB, PxC and PxD. The polarity of the PWM pins is configurable and is selected by setting the CCPxM bits in the CCPxCON register appropriately.

epwmblock.png

PWM Timer Selection

On many newer devices, the designer has several timers to choose from for the PWM peripheral. Timer2/4/6 are a typical set of choices. The PWM Peripheral makes use of one of the 8-bit Timer2/4/6 timer resources to specify the PWM period. The timer selection is controlled by the CxTSEL<1:0> bits in the CCPTMRS register. For a device with four PWM modules, the CCPTMRS register would look like the selections below:

CCPTMRS: PWM Timer Selection Control Register

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
C4TSEL1 C4TSEL0 C3TSEL1 C3TSEL0 C2TSEL1 C2TSEL0 C1TSEL1 C1TSEL0
bit 7 bit 0

bit 7-6

C4TSEL<1:0>: CCP4 Timer Selection bits

00 = CCP4 is based off Timer 2 in PWM Mode
01 = CCP4 is based off Timer 4 in PWM Mode
10 = CCP4 is based off Timer 6 in PWM Mode
11 = Reserved

bit 5-4

C3TSEL<1:0>: CCP3 Timer Selection bits

00 = CCP3 is based off Timer 2 in PWM Mode
01 = CCP3 is based off Timer 4 in PWM Mode
10 = CCP3 is based off Timer 6 in PWM Mode
11 = Reserved

bit 3-2

C2TSEL<1:0>: CCP2 Timer Selection bits

00 = CCP2 is based off Timer 2 in PWM Mode
01 = CCP2 is based off Timer 4 in PWM Mode
10 = CCP2 is based off Timer 6 in PWM Mode
11 = Reserved

bit 1-0

C1TSEL<1:0>: CCP1 Timer Selection bits

00 = CCP1 is based off Timer 2 in PWM Mode
01 = CCP1 is based off Timer 4 in PWM Mode
10 = CCP1 is based off Timer 6 in PWM Mode
11 = Reserved

PWM Start-Up

When any of the EPWM modes are used, the application hardware must use the proper external pull-up and/or pull-down resistors on the PWM output pins for additional current drive. The CCPxM<1:0> bits of the CCPxCON register allow the user to choose whether the PWM output signals are active-high or active-low for each pair of PWM output pins (PxA/PxC and PxB/PxD).

The PWM output polarities must be selected before the PWM pin output drivers are enabled. Changing the polarity configuration while the PWM pin output drivers are enabled is not recommended since it may result in damage to the application circuits.

The PxA, PxB, PxC and PxD output latches may not be in the proper states when the EPWM module is initialized. Enabling the PWM pin output drivers at the same time as the EPWM modes may cause damage to the application circuit.

The EPWM modes must be enabled in the preferred mode and complete a full PWM cycle before enabling the PWM
pin output drivers. The completion of a full PWM cycle can be determined by monitoring the overflow bit for the timer selected to control the EPWM module. This timer overflow (TMRxIF) bit is located in the Peripheral interrupt register (PIRx). The TMRxIF flag will be set as the second PWM period begins.

Alternate Pin Locations

The software design must configure the PWM I/O pin as an output by clearing the associated TRIS bit. Also, on some newer devices, the PWM I/O pin function can be moved to alternative pins using the APFCON0 or APFCON1 registers or through the Peripheral Pin Select feature.

Half-Bridge (PWM)

Half-Bridge mode is an option for Enhanced PWM. In Half-Bridge mode, two ECCP pins are used as outputs to drive push-pull loads. The Enhanced PWM output signal is output on two I/O pins: the PxA pin and the PxB pin. The PxA pin will output one PWM signal while the complementary PWM output signal is output on the PxB pin. The Enhanced PWM will handle the timing of the two alternating PWM signals to drive an H-Bridge arrangement or Full-Bridge, where four power switches are being modulated with two PWM signals.

In Half-Bridge mode, the Enhanced PWM dead-band delay can be used to prevent shoot-through or direct short circuit paths of current in Half-Bridge arrangements.

halfbridgesch.png

I/O Setup

The PxA and PxB outputs are multiplexed standard digital I/O pins and need to be setup as outputs to drive the PWM signal. This is down by clearing the associated bit in the TRIS register.

PWM Dead-Band

In Half-Bridge or Full-Bridge Enhanced PWM applications, if both the upper and lower power circuits are switched at the same time (one turned on, and the other turned off), due to delay in the circuitry, both switches may be on for a short period of time. During this brief interval, a very high current (shoot through current) will flow through both power switches, shorting the bridge supply.

To avoid this potentially destructive shoot-through current from flowing during switching, Dead-Band Delay can be implemented to allow one current path to completely turn off before the other current path is turned on.

The delay occurs at the signal transition from the non-active state to the active state and the delay is adjustable.

The lower seven bits of the associated PWMxCON register set the delay period in units of instruction clock cycles (Fosc/4).
For example, a device running at 4 Mhz will have a 1 Mhz instruction clock or 1 microsecond period. Therefore the value in the PWMxCON register will create a delay between pulses in increments of 1 microsecond.

The image below shows the Dead-Band Delay graphically as the value td.

deadband.png

Full-Bridge (PWM)

When the Enhanced PWM is configured for Full-Bridge mode, four I/O pins are used as PWM outputs. This allows both forward and reverse control of the current through the load, typically a motor.

The PxA, PxB, PxC and PxD I/O pins will be driven as outputs and are multiplexed with digital I/O pins. Therefore, the associated TRIS bits must be cleared to configure the PxA, PxB, PxC and PxD pins as outputs.

fullbridgesch.png

DIRECTION CHANGE

The PxM1 bit in the CCPxCON register controls the forward/reverse direction. When the application firmware changes this direction control bit, the module will change to the new direction on the next PWM cycle.

In the Forward direction mode, the pin PxA is driven to its active state, and the pin PxD is modulated, while PxB and PxC will be driven to their inactive state.

In the Reverse direction mode, PxC is driven to its active state and the pin PxB is modulated, while PxA and PxD will be driven to their inactive state.

When changing direction, the following sequence occurs four Timer2 cycles prior to the end of the current PWM period:

  • The modulated outputs (PxB and PxD) are placed in their inactive state.
  • The associated unmodulated outputs (PxA and PxC) are switched to drive in the opposite direction.
  • PWM modulation resumes at the beginning of the next period.
direction.png

DEAD-BAND DELAY

The Full-Bridge mode on the Enhanced PWM does not provide dead-band delay. Since only one output is modulated at a time, dead-band delay is generally not required. There are rare situations where dead-band delay is required. This situation occurs when both of the following conditions are true:

1. The direction of the PWM output changes when the duty cycle of the output is at or near 100%.
2. The turn-off time of the power switch, including the power device and driver circuit, is greater than the turn-on time.

In the 100% duty cycle waveforms below, at time t1, the output PxA and PxD become inactive, while at the same time output PxC becomes active. This can cause a short period of shoot-through current.

Two possible solutions for eliminating the shoot-through current are:

1. Reduce PWM duty cycle for one PWM period before changing directions.
2. Use switch drivers that can drive the switches off faster than they can drive them on.

deadband.png

Auto-Shutdown/Auto-Restart

The Enhanced PWM mode supports Auto-Shutdown mode and Auto-Restart mode.

autoshut_restart.png

Figure 1: Waveform showing the Auto-Shutdown/Auto-Restart

Auto-Shutdown

Auto-Shutdown will disable the PWM outputs when an external shutdown event occurs and places the PWM output pins into a predetermined state. This mode is used to help prevent the PWM from damaging the application. The auto-shutdown sources are selected using the CCPxAS<2:0> bits of the CCPxAS register. A shutdown event may be generated by:

  • A logic ‘0’ on the INT pin
  • A logic ‘1’ on a Comparator (Cx) output

A shutdown condition is indicated by the CCPxASE (Auto-Shutdown Event Status) bit of the CCPxAS register.

  • If the bit is a ‘0’, the PWM pins are operating normally.
  • If the bit is a ‘1’, the PWM outputs are in the shutdown state.

When a shutdown event occurs, two things happen:

1) The CCPxASE bit is set to ‘1’. The CCPxASE will remain set until cleared in firmware or an auto-restart occurs.

2) The enabled PWM pins are asynchronously placed in their shutdown states. The PWM output pins are grouped into pairs [PxA/PxC] and [PxB/PxD]. The state of each pin pair is determined by the PSSxAC and PSSxBD bits of the CCPxAS register. Each pin pair may be placed into one of three states:

  • Drive logic ‘1’
  • Drive logic ‘0’
  • Tri-state (high-impedance)

In the Figure 1 waveform plot above, the Shut-Down occurs at the "Shutdown Event Occurs" label. This is caused by the Comparator Output going to a high state.

Auto-Restart

The Enhanced PWM can be configured to automatically restart the PWM signal once the auto-shutdown condition has been removed. Auto-restart is enabled by setting the PxRSEN bit in the PWMxCON register.

If auto-restart is enabled, the CCPxASE bit will remain set as long as the auto-shutdown condition is active.

When the auto-shutdown condition is removed, the CCPxASE bit will be cleared via hardware and normal operation will resume.

This can be seen in Figure 1 above where the "PWM Resumes" label is shown. The Auto-Restart actually occurs right after the CCPxASE is cleared but the PWM waveform cannot start until a full pulse can be released.

PWM Steering

When the Enhanced PWM is enabled in single output mode, the PxA I/O pin will drive the pulse width modulated signal. However, that can be directed to other PWM I/O pins through the Steering Mode option.

PWM steering allows any of the PWM pins to be set as a the modulated signal. Additionally, the same PWM signal can be simultaneously available on multiple PWM pins. The PWM auto-shutdown option works on all the enabled PWM I/O pins.

pwmio.png


Single Output Mode

The Single Output mode is selected by the PxM<1:0> bits in the CCPxCON register. The module has to also be in the EPWM mode which is any of the Enhanced PWM mode selections in the CCPxCON register.

CCPxCON: CCPx Control Register

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PxM1 PxM0 DCxB1 DCxB0 CCPxM3 CCPxM2 CCPxM1 CCPxM0
bit 7 bit 0

bit 7-6

PxM<1:0>: Enhanced PWM Output Configuration Bits

00 = Single output; PxA modulated; PxB, PxC, PxD assigned as port pins
01 = Full-Bridge output forward; PxD modulated; PxA active; PxB, PxC inactive
10 = Half-Bridge output; PxA, PxB modulated with dead-band control; PxC, PxD assigned as port pins
11 = Full-Bridge output reverse; PxB modulated; PxC active; PxA, PxD inactive

bit 3-0

CCPxM<3:0>: ECCP Mode Select bits

1100 = PWM mode: PxA, PxC active-high; PxB, PxD active-high
1101 = PWM mode: PxA, PxC active-high; PxB, PxD active-low
1110 = PWM mode: PxA, PxC active-low; PxB, PxD active-high
1111 = PWM mode: PxA, PxC active-low; PxB, PxD active-low


Steering Mode Setting

Routing a PWM signal to a different I/O pin, or more than one I/O pin, can be accomplished with the PWM Steering option. By setting the associated bit for each PWM I/O pin in the PSTRxCON register, the PWM output can be directed to the specific I/O pin.

PSTRxCON: PWM Steering Control Register

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
STRxSYNC STRxD STRxC STRxB STRxA
bit 7 bit 0

bit 3

STRxD: Steering Enable bit D

1 = PxD pin has the PWM waveform with polarity control from CCPxM<1:0>
0 = PxD pin is assigned to port pin

bit 2

STRxC: Steering Enable bit C

1 = PxC pin has the PWM waveform with polarity control from CCPxM<1:0>
0 = PxC pin is assigned to port pin

bit 1

STRxB: Steering Enable bit B

1 = PxB pin has the PWM waveform with polarity control from CCPxM<1:0>
0 = PxB pin is assigned to port pin

bit 0

STRxA: Steering Enable bit A

1 = PxA pin has the PWM waveform with polarity control from CCPxM<1:0>
0 = PxA pin is assigned to port pin


Steering Synchronization

The Enhanced PWM Steering can control when the PWM signal will update via the Synchronization settings.
The STRxSYNC bit of the PSTRxCON register provides the user two options for when the steering event will occur.

When the STRxSYNC bit is ‘0’, the steering event will happen at the end of the instruction that writes to the PSTRxCON register. In this case the output signal at the Px<D:A> pins may be an incomplete PWM waveform. This operation is useful when the user firmware needs to immediately remove a PWM signal from the pin.

When the STRxSYNC bit is ‘1’, the effective steering update will happen at the beginning of the next PWM period. In this case steering ON/OFF of the PWM output will always produce a complete PWM waveform.

PSTRxCON: PWM Steering Control Register

U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
STRxSYNC STRxD STRxC STRxB STRxA
bit 7 bit 0

bit 4

STRxSYNC: Steering Sync bit

1 = Output steering update occurs on next PWM period
0 = Output steering update occurs at the beginning of the instruction cycle boundary

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