CLCxGLSn Registers

The CLCxGLSn registers, contained in the Configurable Logic Cell (CLC), control the polarity of the selected CLC inputs.

CLC Data Gating

Outputs from the input multiplexers are directed to the desired logic function input through the data gating stage. Each data gate can direct any combination of four selected inputs. The gate can be configured to direct each input signal as inverted or non-inverted data. Directed signals are ORed together in each gate. The output of each gate can also be inverted before going on to the logic function stage but that is controlled by the CLCxPOL register.

The Data Gating section is controlled by one of four registers. Each gate has a separate register. Each input has an "N" bit and a "P" bit. Setting the "N" bit inverts the input and setting the "P" bit makes it non-inverted. If neither is set, the gate will be a constant logic level high or low depending on the output polarity setting in:

  • CLCxGLS0
  • CLCxGLS1
  • CLCxGLS2
  • CLCxGLS3

CLCxGLS0 is shown in Figure 1

Figure 1

From the PIC16F1507 Datasheet.

Creating Various Gates

Each data gate is, in essence, a 1-to-4 input AND/NAND/OR/NOR gate depending on the invert/non-invert settings. When every input is inverted and the output is inverted, the gate is a NOR of all enabled data inputs. When the inputs and output are not inverted, the gate is an OR of all enabled inputs.

The table shown in Figure 2 summarizes the basic logic that can be obtained in a gate by using the gate logic select bits.

Figure 2

The table shows the logic of four input variables. However, each gate can be configured to use less than four. If no inputs are selected, the output will be 0 or 1 - depending on the gate output polarity bit. The output polarity is controlled by the register.

Figure 3
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