CWG: Complementary Waveform Generator

The Complementary Waveform Generator (CWG) produces a complementary waveform with dead-band delay from a selection of input sources.

The CWG module has the following features:

  • Selectable dead-band clock source control
  • Selectable input sources
  • Output enable control
  • Output polarity control
  • Dead-band control with independent 6-bit rising and falling edge dead-band counters
  • Auto-shutdown control with:
    • Selectable shutdown sources
    • Auto-restart enable
    • Auto-shutdown pin override control

The CWG generates a two output complementary waveform from one of several selectable input sources. The off-to-on transition of each output can be delayed from the on-to-off transition of the other output, thereby creating a time delay immediately where neither output is driven. This is referred to as dead time or dead band and is covered in Section below titled “Dead-Band Control”.

It may be necessary to guard against the possibility of circuit faults. In this case, the active drive may be terminated before the Fault condition causes damage. This is referred to as auto-shutdown and is covered in Section below “Auto-shutdown Control”.

cwg.png

The CWG requires five sections to be setup:

  • Input
  • Clock
  • Dead Band
  • Shutdown
  • Output Control

CWG Video Tutorial

This video will introduce the Complimentary Waveform Generator (CWG) for Microchip 8-bit MCU devices and show how to use it.


Input Source

The CWG offers several input sources to generate the complementary waveform. This may vary from device to device. The list below is from the PIC16F1507 device. The list includes:

• PWM1 (Pulse Width Modulated Output 1)
• PWM2 (Pulse Width Modulated Output 2)
• PWM3 (Pulse Width Modulated Output 3)
• PWM4 (Pulse Width Modulated Output 4)
• N1OUT (Numerically Controlled Oscillator Output)
• LC1OUT (Configurable Logic Cell Output)

The input source is selected using the GxIS<2:0> bits in the CWGxCON1 register.

Some devices also include the output from a comparator module as input to the CWG. It's best to refer to the Data Sheet for the device you are using for the updated list of selected input choices.

inputs.png
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Clock Source

The CWG module allows for one of two clock sources to be selected:

• Fosc (system clock)
• HFINTOSC (16 MHz only)

The clock sources are selected using the G1CS0 bit of the CWGxCON0 register.

clocksource.png
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Dead-Band Control

Dead-band control provides for non-overlapping output signals, to prevent shoot through current in power switches. The CWG contains two 6-bit dead-band counters (CWGxDBR and CWGxDBF registers). One dead-band counter is used for the rising edge of the input source control while the other is used for the falling edge of the input source control.

Dead-band is timed by counting CWG clock periods from zero up to the value in the rising or falling dead-band counter registers.

deadband.png
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Rising Edge Control

The rising edge dead-band delays the turn-on of the CWGxA output from when the CWGxB output is turned off. The rising edge dead-band time starts when the rising edge of the input source signal goes true. When this happens, the CWGxB output is immediately turned off and the rising edge dead-band delay time starts. When the rising edge dead-band delay time is reached, the CWGxA output is turned on.

The CWGxDBR register sets the duration of the dead-band interval on the rising edge of the input source signal. This duration is from 0 to 64 counts of dead band. Dead band is always counted off the edge on the input source signal. A count of 0 (zero), indicates that no dead-band is present. If the input source signal is not present for enough time for the count to be completed, no output will be seen on the respective output.

risefall.png
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Falling Edge Control

The falling edge dead band delays the turn-on of the CWGxB output from when the CWGxA output is turned off. The falling edge dead-band time starts when the falling edge of the input source goes true. When this happens, the CWGxA output is immediately turned off and the falling edge dead-band delay time starts. When the falling edge dead-band delay time is reached, the CWGxB output is turned on.

The CWGxDBF register sets the duration of the deadband interval on the falling edge of the input source signal.
This duration is from 0 to 64 counts of dead band. Dead band is always counted off the edge on the input
source signal. A count of 0 (zero), indicates that no dead band is present. If the input source signal is not present for enough time for the count to be completed, no output will be seen on the respective output.

dbexample.png
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Dead-Band Uncertainty

When the rising and falling edges of the input source trigger the dead-band counters, the input may be asynchronous to the clock input. This will create some uncertainty in the dead-band time delay. The maximum uncertainty is equal to one CWG clock period.

uncertainty.png
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Auto-shutdown Control

Auto-shutdown is a method to immediately override the CWG output levels with specific settings that allow for
safe shutdown of the circuit. The shutdown state can be either cleared automatically or held until cleared by
software.

The shutdown state can be entered by either of the following
two methods:

  • Software generated
  • External Input

Software Generated

Setting the GxASE bit of the CWGxCON2 register will force the CWG into the shutdown state. When auto-restart is disabled, the shutdown state will persist as long as the GxASE bit is set. When auto-restart is enabled, the GxASE bit will clear automatically and resume operation on the next rising edge event.

External shutdown signals provide the fastest way to safely suspend CWG operation in the event of a Fault condition. When any of the selected shutdown signals goes active, the CWG outputs will immediately go to the selected override levels without software delay. Any combination of two shutdown signals can be selected to cause a shutdown condition. The shutdown signals offered may vary with the device being used but those shutdown sources are selected by the GxASDS0 and GxASDS1 bits of the CWGxCON2 register.

shutdown.png
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Output Control

Output Pin Enable

Each CWG output pin has individual output pin enable control. Output enables are selected with the GxOEA and GxOEB bits of the CWGxCON0 register. When an output pin enable is cleared, the CWG has no connection to the output pin. When the output enable is set, the override value or active PWM waveform is applied to the pin per the internal port priority selection.

The CWG function can be completely disabled by clearing the GxEN pin in the CWGxCON0 register.

outputs.png
Click image to enlarge.

Polarity Control

The polarity of each CWG output can be selected independently. When the output polarity bit is set, the corresponding output is active high. Clearing the output polarity bit configures the corresponding output as active low. However, polarity does not affect the override levels. Output polarity is selected with the GxPOLA and GxPOLB bits of the CWGxCON0 register.

outputpolarity.png
Click image to enlarge.

Operation During Sleep Mode

The CWG module operates independently from the system clock and will continue to run during Sleep, provided that the clock and input sources selected remain active. The HFINTOSC remains active during Sleep, provided that the CWG module is enabled, the input source is active, and the HFINTOSC is selected as the clock source, regardless of the system clock source selected.

In other words: if the HFINTOSC is simultaneously selected as the system clock and the CWG clock source, then when the CWG is enabled and the input source is active the CPU will go idle during Sleep, but the CWG will continue to operate and the HFINTOSC will remain active. This will have a direct effect on the Sleep mode current.

CWG Example

Sometimes its helpful to step through an example.
Click on the link below to see a step by step example of using the CWG Module
CWG Example.

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