CLCxCON Register

The Output section and the Logic section of the Configurable Logic Cell (CLC) are controlled by the CLCCON Register.

CLCxCON: Configurable Logic Cell Control Register

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0
LCxEN LCxOE LCxOUT LCxINTP LCxINTN LCxMODE2 LCxMODE1 LCxMODE0
bit 7 bit 0
Legend
R = Readable Bit W = Writable Bit U = Unimplemented bit, read as '0'
u = Bit is unchanged x = bit is unknown -n/n = Value at POR and BOR/Value at all other resets
'1' = bit is set '0' = bit is cleared -n = Value at POR reset

bit 7

LCxEN: Configurable Logic Cell Enable bit

1 = Configurable logic cell is enabled and mixing input signals
0 = Configurable logic cell is disabled and has logic zero output

bit 6

LCxEOE: Configurable Logic Cell Output Enable bit

1 = Configurable logic cell port pin output enabled
0 = Configurable logic cell port pin output disabled

bit 5

LCxOUT: Configurable Logic Cell Data Output bit

Read-only: logic cell output data, after LCxPOL; sampled from lcx_out wire

bit 4

LCxINTP: Configurable Logic Cell Positive Edge Going Interrupt Enable bit

1 = LCxIF will be set when a rising edge occurs on lcx_out
0 = LCxIF will not be set

bit 3

LCxINTN: Configurable Logic Cell Negative Edge Going Interrupt Enable bit

1 = LCxIF will be set when a falling edge occurs on lcx_out
0 = LCxIF will not be set

bit 2-0

LCxMODE<2:0>: Configurable Logic Cell Functional Mode bits

111 = Cell is 1-input transparent latch with S and R
110 = Cell is J-K Flip-Flop with R
101 = Cell is 2-input D Flip-Flop with R
100 = Cell is 1-input D Flip-Flop with S and R
011 = Cell is S-R latch
010 = Cell is 4-input AND
001 = Cell is OR-XOR
000 = Cell is AND-OR

from PIC16F1507 Data Sheet.


The CLC Enable bit will enable or disable the CLC module. A 1 enables it and a 0 disables it.

LCEN.png

The CLC Output Enable bit will enable or disable the CLC module output. A 1 enables it and a 0 disables it.

LCOE.png

The CLC LCOUT bit is a flag that can be monitored in software to determine the state of the CLC output.

LCOUT.png

The CLC LCINTP bit enables the rising edge interrupt in the CLC. When enabled (set to a 1) the CLC will trigger an interrupt when the CLC output rises from low to high state.

LCINTP.png

The CLC LCINTN bit enables the falling edge interrupt in the CLC. When enabled (set to a 1) the CLC will trigger an interrupt when the CLC output falls from high to low state.

LCINTN.png

The CLC LCMODE bits select the CLC Logic Function using three bits (0-2).

LCMODE.png

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