CLCxPOL Register

The CLCxPOL register, contained in the Configurable Logic Cell (CLC), controls the polarity of the data gating outputs and also the polarity of the CLC output.

CLC Data Gate Outputs

The following image summarizes the basic logic that can be obtained in a gate by using the gate logic select bits.


The table shows the logic of four input variables, but each gate can be configured to use less than four. If no inputs are selected, the output will be 0 or 1, depending on the gate output polarity bit. The output polarity is controlled by the CLCxPOL register.


CLC Output Control

The output of the entire CLC can also be inverted in the CLCxPOL register by setting the seventh bit in the register. Clearing the bit will make the CLC output non-inverted.


1 - Invert the CLC output
0 - Non-invert the CLC output

© 2024 Microchip Technology, Inc.
Notice: ARM and Cortex are the registered trademarks of ARM Limited in the EU and other countries.
Information contained on this site regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.