Hardware Limit Timer - Interrupts

The Hardware Limit Timer (HLT) can also generate an optional device interrupt. The HLTMRx output signal provides the input for the 4-bit postscaler. The overflow output of the postscaler sets the HLTMRxIF bit of the Peripheral Interrupt Register (PIR1).

The interrupt is enabled by setting the HLTMRx Match Interrupt Enable bit (HLTMRxIE) of the Peripheral Interrupt Enable Register (PIE1).

Only devices that have the HLT peripheral will have the Interrupt Enable bits. For mor information on 8-Bit PIC® MCU Interrupts visit the Interrupts Training Module.

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