Hardware Limit Timer - Interrupts

The Hardware Limit Timer (HLT) can also generate an optional device interrupt. The HLTMRx output signal provides the input for the 4-bit postscaler. The overflow output of the postscaler sets the HLTMRxIF bit of the Peripheral Interrupt Register (PIR1).

The interrupt is enabled by setting the HLTMRx Match Interrupt Enable bit (HLTMRxIE) of the Peripheral Interrupt Enable Register (PIE1).

Only devices that have the HLT peripheral will have the Interrupt Enable bits. For mor information on 8-Bit PIC® MCU Interrupts visit the Interrupts Training Module.

© 2017 Microchip Technology, Inc.
Information contained on this site regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.