Hardware Limit Timer

Hardware Limit Timer (HLT)

Hardware Limit Timer (HLT) module is a watchdog timer designed for the Complimentary Output Generator (COG) but its interrupt output can be used to trigger other actions. It has a set point and a running counter that is incremented by the system instruction clock (Fosc/4). When the running counter value matches the set point, the output of the HLT triggers an external shutdown input to the COG module operation. External shutdown inputs provide the fastest way to safely suspend COG operation in the event of a fault condition. The match also triggers an interrupt which can then be used in an interrupt service routine to take action on other peripherals.

The structure of the HLT is similar to a Timer 2 module as seen in the lower portion of the block diagram below. The upper portion shows the signals that can cause the HLT to reset the incremental counter.

hlt1.png

Hardware Limit Timer (HLT) Operation

The Hardware Limit Timer (HLT) is similar to any PIC® MCU Timer 2 module. The clock input to the HLT module is the system instruction clock (Fosc/4). The Hardware Limit Timer Register (HLTMRx) increments on each rising clock edge. The value of HLTMRx register is compared to that of the Hardware Limit Timer Period register (HLTPRx), on each clock cycle. When the two values match, the comparator generates a match signal as the HLTimerx output. This signal also resets the value of HLTMRx to 00h on the next clock rising edge and drives Complimentary Output Generator (COG) output along with the output counter/postscaler.

hlt6.png

The HLT can be turned off or on at any point by clearing or setting the HLT On bit in the Hardware Limit Timer Control Register 0 (HLTxCON0). The clock input to the HLT can be slowed down by the use of the optional 4-bit counter/prescaler at the clock input. This prescaler provides the following prescale options:

• Divide-by-1
• Divide-by-4
• Divide-by-16
• Divide-by-64

The prescale options are selected by the prescaler control bits, HxCKPS<1:0> of the HLTxCON0 register. The output of the HLT can be directed to the COG module and also to the HLT output postscaler. The postscaler can also be set to delay the HLT Interrupt from 1 match on up to 16 matches. This is selected by the HxOUTPS<3:0> bits in the HLTxCON0 register.

HLTxCON0: HARDWARE LIMIT TIMER CONTROL REGISTER 0

hlt2.png
hlt3.png

The HLTMRx and HLTPRx registers are both directly readable and writable. The HLTMRx register is cleared on any device Reset, whereas the HLTPRx register initializes to FFh. Both the prescaler and postscaler counters are cleared on any of the following events:

  • A write to the HLTMRx register
  • A write to the HLTxCON0 register
  • Power-on Reset (POR)
  • Brown-out Reset (BOR)
  • MCLR Reset
  • Watchdog Timer (WDT) Reset
  • Stack Overflow Reset
  • Stack Underflow Reset
  • RESET Instruction

Hardware Limit Timer (HLT) Reset Options

Hardware Limit Timer (HLT) can be reset by several selected peripheral outputs to prevent the HLTMRx from matching the HLTPRx register and generating an output. In this manner, the HLT can be used as a hardware time limit to other peripherals.

The HLTMRx can be reset by one of several selectable peripheral sources.

  • CCP1 output
  • Comparator 1 output
  • Comparator 2 output
  • COGxFLT pin
  • COG1OUT0
  • COG1OUT1

The HLT can be reset by various external sources which are selected via the HLT External Reset Sources Select bits (HxERS <2:0>) in the HLT Control Register 1 (HLTxCON1). The edge sensitivity can also be selected with the HLTxCON1 register. High and Low Reset enables are selected with the HxREREN and HxFEREN bits, respectively. Setting the HxRES and HxFES bits makes the respective rising and falling reset events edge sensitive. Reset inputs that are not edge sensitive are level sensitive.

HLTMRx resets are synchronous with the HLT clock. In other words, HLTMRx is cleared on the rising edge of the HLT clock after the enabled reset event occurs. If an enabled external reset occurs at the same time as a write occurs to the HLTMRx register, the write to the timer takes precedence and pending resets are cleared.

HLTxCON1: HARDWARE LIMIT TIMER CONTROL REGISTER 1

hlt4.png
hlt5.png

HLT Operation During Sleep

The HLT cannot be operated while the processor is in Sleep mode. The contents of the HLTMRx register will remain unchanged while the processor is in Sleep mode.

Hardware Limit Timer (HLT) Interrupt

The Hardware Limit Timer (HLT) can also generate an optional device interrupt. The HLTMRx output signal provides the input for the 4-bit postscaler. The overflow output of the postscaler sets the HLTMRxIF bit of the Peripheral Interrupt Register (PIR1).

The interrupt is enabled by setting the HLTMRx Match Interrupt Enable bit (HLTMRxIE) of the Peripheral Interrupt Enable Register (PIE1).

Only devices that have the HLT peripheral will have the Interrupt Enable bits. For mor information on 8-Bit PIC® MCU Interrupts visit the Interrupts Training Module.

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