The 4x PLL is an added feature on newer PIC® MCU device that allows the oscillator frequency to be multiplied by a 4x factor. This will allow an internal or external oscillator to run at a slower speed and still get four times the speed for the system clock. This becomes very handy to correct the instruction clock divide by four factor (Fosc/4). An 8 Mhz external crystal can be boosted up through the 4x PLL to 32 Mhz and then the Fosc/4 circuitry used for the internal instruction clock will reduce it back down to 8 Mhz. This results in an instruction clock that matches the speed of the external oscillator.
Another advantage of this slower clock is less power draw for the oscillator drive while getting the higher speed through the 4x PLL.
The 4x PLL is shown in the Oscillator structure below. The Fosc signal can supply the system clock or the output from the PLL can supply the system clock (Fsys). The PLLMUX and the PRIMUX settings are controlled by the 4x PLL setup and the Oscillator selected.
4x PLL Input Range
The 4x PLL has a limited range for the input frequency and the data sheet for the device should be consulted to verify, but for many devices the max input is 8 Mhz which results in a 32 Mhz maximum output frequency.
The PIC16F1713/6 specification shows a range of 4 - 8 Mhz input range for the 4x PLL as shown in the chart below.
4x PLL Setup
The 4x PLL can be enabled in one of two ways; a configuration bit setting (PLLEN) at program time or a software enabled bit (SPLLEN) during run time. The Configuration setting is the higher priority. If the PLLEN bit is set to a one in the configuration register then the software setting is ignored as the 4x PLL will always be enabled and cannot be disabled unless the device is reprogrammed and the PLLEN bit is set to zero.
To set the 4x PLL on permanently, the PLL Enable bit (PLLEN) in a configuration register can be set to a one to enable the 4x PLL. The Fosc selection will be routed through the 4x PLL and the output will become the system clock. The input requirements for the 4x PLL must be met as described in the section above and detailed in the electrical section of the data sheet.
To set the 4x PLL via software, the Software PLL Enable bit (SPLLEN) in the OSCCON register can be set to a one to enable the 4x PLL. The Fosc selection will be routed through the 4x PLL and the output will become the system clock. The input requirements for the 4x PLL must be met as described in the section above and detailed in the electrical section of the data sheet.