Timer1 Gate

The Timer1 Gate feature allows the PIC MCU device to easily time external events using T1G pin as the input or analog events using an internal Comparator. This can be useful for timing the high pulse time of a waveform. The Timer1 Gate can control when the Timer1 increments. It is essentially an on/off switch for the Timer1 counter. There are several individual bits in the Timer1 Gate Control register (T1GCON register) that control the operation of the Timer1 Gate. Each setting is covered below.



The Timer1 Gate is enabled by setting the Timer1 Gate Enable bit (TMR1GE bit) of the T1GCON register. This enables control of the Timer1 count from an external source such as the T1G I/O pin or several other sources.


The Timer1 Gate Value Status bit (T1GVAL bit) indicates when the Timer1 is active by being set high or a 1. When the gate control halts the Timer1 operation, then the T1GVAL bit will clear.


The polarity of the Timer1 Gate is configured using the Timer1 Gate Polarity bit (T1GPOL bit) of the T1GCON. Setting this bit high will enable Timer1 counting when the T1G pin is also high. Setting this bit low will enable Timer1 counting when the T1G pin is low.


Timer1 gate has several source selections beyond the T1G i/O pin for controlling the Timer1 Gate depending on the PIC MCU device being used. The options may include:

11 - Comparator 2 Output
10 - Comparator 1 Output
01 - Timer0 Overflow
00 - T1G I/O Pin

The two bits preceding the selections above are the two Timer1 Gate Source Select bits (T1GSS bits) of the T1CON register that select the control option.

Both Comparator outputs can start or stop the Timer1 count based on the output signal level as it compares to the Timer1 Gate polarity setting. When the output matches the polarity setting, the Timer1 count will increment on its clock source signal. When the output is opposite the polarity setting, then the Timer1 count is halted.

The Timer0 overflow will send a high signal to the Timer1 Gate circuitry when Timer0 overflows from FFh to 00h. The Timer1 Gate Polarity setting will determine if the Timer1 starts to count (T1GPOL = 1) on the overflow signal or stops (T1GPOL = 0) on the overflow signal.

The T1G pin is a direct source for Timer1 gate control. It can be used to supply an external signal to control the Timer1 operation.



Timer1 Gate also has the option of a Toggle Mode. Timer1 Gate Toggle mode is enabled by setting the Timer1 Gate Toggle Mode bit (T1GTM bit) of the T1GCON register. The Toggle Mode allows the Timer1 control to be based on alternating control signals.

When the Timer1 Gate control signal matches the polarity setting, the Timer1 will start incrementing. When the Timer1 Gate control signal toggles to the opposite polarity, the Timer1 will be allowed to continue incrementing until the Timer1 control signal matches the polarity a second time. At that point the Timer1 will stop incrementing and hold the value. This allows the Timer1 to measure the period of an alternating signal.



Timer1 Gate Single-Pulse Mode enables the time capture of a single-pulse event. Timer1 Gate Single-Pulse mode is first enabled by setting the Timer1 Gate Single Pulse Mode bit (T1GSPM bit) in the T1GCON register. Next, the Timer1 Gate Go/Done bit (T1GGO/DONE bit) in the T1GCON register must be set to a 1. The Timer1 will begin counting on the next incrementing edge of the Timer1 Gate Source signal thus beginning the measurement of a pulse.

On the following trailing edge of the pulse being measured, the T1GGO/DONE bit will automatically be cleared and the Timer1 count will be halted. The TMR1 register will contain the pulse width time measurement in timer counts. No other gate events will be allowed to increment Timer1 until the T1GGO/DONE bit is once again set in software so the application can retrieve the value from the TMR1 register.

If the Single-Pulse Gate mode is disabled by clearing the T1GSPM bit in the T1GCON register, the T1GGO/DONE
bit should also be cleared.



Enabling the Toggle mode and the Single-Pulse mode simultaneously will permit both sections to work together. This allows a full cycle to be captured and then the Timer1 halted with the total period time of the waveform.



An interrupt can be generated by the Timer1 Gate structure. The Interrupt is based on the T1GVAL bit in the T1GCON register. When the falling edge of T1GVAL occurs, the Timer1 Gate Interrupt Flag bit (TMR1GIF flag bit) in the Peripheral Interrupt Register 1 (PIR1) will be set. If the Timer1 Gate Interrupt Enable bit (TMR1GIE bit) in the Peripheral Interrupt Enable Register 1 (PIE1) is set, enabling the interrupt, then an interrupt will be recognized and a redirect to the interrupt service routine will occur.

PIR1 Register

The TMR1GIF flag bit can be polled without enabling the Timer1 Gate interrupt, as the TMR1GIF flag bit operates even when the Timer1 gate interrupt is not enabled.

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