Timer1 Interrupt

Timer1 can trigger an interrupt when it overflows from FFFFh to 0000h. When Timer1 rolls over, the Timer1 Interrupt Flag (TMR1IF) bit of the Peripheral Interrupt 1 Register (PIR1) is set. Timer1 overflow can be monitored by randomly checking the TMR1IF bit.

An automatic interrupt can be enabled to redirect operation to the Interrupt Service Routine (ISR) as soon as Timer1 overflows. To enable the automatic interrupt on rollover, you must set these bits:

  • TMR1ON bit of the T1CON register
  • TMR1IE bit of the PIE1 register
  • PEIE bit of the INTCON register
  • GIE bit of the INTCON register
​

Note: For more information on the interrupt structure for 8-Bit devices, refer to the Enhanced Mid-Range Interrrupts training module.

The interrupt is cleared by clearing the TMR1IF bit in the ISR.

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