Timer2 Operation

Timer2 is driven by the internal instruction clock (FOSC/4). The Timer2 register (TMR2) increments on each clock edge. A prescaler on the clock input allows direct input (1:1), divide-by-4, divide-by-16 and on some devices divide-by-64 prescale options. These options are selected by the prescaler control bits, T2CKPS of the Timer2 Control register (T2CON). The value of TMR2 is compared to that of the Period register (PR2) on each clock cycle. When the two values match, the comparator generates a match signal as the timer output for other peripherals to use as a time base. A Timer2 interrupt can also be triggered by the match. The match signal becomes the input to an optional postscaler and also resets the value of TMR2 to 00h on the next cycle.


The TMR2 and PR2 registers are both directly readable and writable. The TMR2 register is cleared on any device Reset, whereas the PR2 register initializes to FFh. Both the prescaler and postscaler counters are cleared on the following events:

  • a write to the TMR2 register
  • a write to the T2CON register
  • Power-on Reset (POR)
  • Brown-out Reset (BOR)
  • MCLR Reset
  • Watchdog Timer (WDT) Reset
  • Stack Overflow Reset
  • Stack Underflow Reset
  • RESET Instruction

Timer2 can be turned on and off via the TMR2ON bit of the Timer2 Control Register.

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