2-Pole/ 2-Zero (2P2Z) Compensator

The 2-Pole/ 2-Zero (2P2Z) Compensator is the digital implementation of the analog type II controller. It is a filter which introduces a specific gain and phase boost into the system by considering two poles and one zero, see the figure below - 2P2Z Compensator Phase and Gain Characteristics. You must strategically select the frequency placement for each of the poles and the zero that will help achieve the desired system performance. In this figure, the (-1) slope is the equivalent to -20 dB/decade and the (+1) slope to +20 dB/decade.


The 2P2Z compensator transfer function below shows the mathematical transfer function for the 2P2Z compensator:


The 2P2Z Compensator Design window is shown in the figure below. In this window, you must enter the specific information about the hardware configuration along with compensator settings. This includes:

  • Poles / Zero Frequency: The location in the frequency domain where the poles or zero should be placed.
  • Pulse-Width Modulation (PWM) Switching Frequency: This is the operating frequency of the power switch (e.g., MOSFET) and this will be defined by the microcontroller Time Base Period Register.
  • PWM Sampling Ratio: The Digital Compensator Design Tool (DCDT) will use this value to calculate the sampling frequency as a function of the PWM Switching Frequency.
    • Sampling Frequency = ( PWM Switching Frequency / PWM Sampling Ratio)
    • For example, use the Trigger # Output Divider bits to configure trigger event register and enable specific hardware sampling frequency, see the dsPIC33/PIC24 Family Reference Manuals for more details.
  • PWM Maximum Resolution: Depending on hardware configuration settings, the PWM resolution will change. This value will be used to compute the PWM gain value, see the dsPIC33/PIC24 Family Reference Manuals for more details.
  • Computational Delay: This is the time it takes for the microcontroller to execute the selected compensator mathematical algorithm, the DCDT will use the default values as defined in Table 2 of the DCDT Default Values page. It is important for you to understand that this delay will not impact the calculated digital compensator coefficients, but it will have an impact on the overall system loop gain (closed-loop) phase margin.
  • Gate Drive Delay: This is the delay associated with the hardware gate-driver + MOSFET delays, (see the section on GUI default values). It is important for you to understand that this delay will not have an impact on the calculated digital compensator coefficients, but it will impact the overall system loop gain (closed-loop) phase margin.
  • Control Output Min/Max: These are integer values that will be used as the absolute max/min clamping limits for the compensator output, this value clamps the value written to the target register and will have no effects to the internal compensator computations.
  • Load Defaults: This button option will load the DCDT default values for the selected compensator (see the section on GUI default values).
  • Use Radian Per Second: Enabling this option allows you to input the poles and zeros location using radians per second (Rad/sec) instead of using Hertz (Hz). It should be noted that no other parameters or bode plots would be represented in radians per second.
  • Enable Frequency Warp: This feature will enable each of the pole/zero frequencies to be pre-warped to ensure correct placement when mapped in the s-plane and that is bounded by the Nyquist frequency (FNyquist = Sampling Frequency /2).
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