Type II Analog Compensator

This compensator was designed to aid power supply designers transition a type II analog compensator that uses resistors, capacitors, and one operational amplifier circuit into a digital compensator to produce a specific frequency response filter. (A type II analog compensator circuit is shown below.) You can enter the values of the resistors and capacitors in the Digital Compensator Design Tool (DCDT) and based on these values, the DCDT will calculate the corresponding location of the compensator two poles and one zero. You can choose to generate the coefficients for the equivalent digital compensator or use these calculations as the starting point to further optimize the performance of the compensator.


The Type II Analog Compensator Design window is shown below. In this window, you must enter the specific information about the hardware configuration along with compensator settings, this includes:

  • Resistor/Capacitor Values: Define component values for the resistor and capacitors as shown on the circuit diagram.
  • Pole / Zeros Frequency: Based on the component values for the resistors and capacitors, the DCDT will calculate the frequency location of the poles and the zeros. If you want to optimize the compensator by adjusting the pole/zeros frequencies, you must enable the Pole/Zero checkbox. The resistor and capacitor component values will not be recalculated based on the pole/zero frequency placement.
  • Pulse Width Modulation (PWM) Switching Frequency: This is the operating frequency of the power switch (e.g., Metal–Oxide–Semiconductor Field-Effect Transistor, also known as MOSFET) and this will be defined by the microcontroller's Time Base Period Register.
  • PWM Sampling Ratio: The DCDT will use this value to calculate the sampling frequency as a function of the PWM Switching Frequency
    • Sampling Frequency = (PWM Switching Frequency / PWM Sampling Ratio)
    • For example, use the Trigger # Output Divider bits to configure the trigger event register and enable a specific hardware sampling frequency, see the dsPIC33/PIC24 Family Reference Manuals for more details.
  • PWM Maximum Resolution: Depending on hardware configuration settings, the PWM resolution will change. This value will be used to compute the PWM gain value, see the dsPIC33/PIC24 Family Reference Manuals for more details.
  • Computational Delay: This is the time it takes for the microcontroller to execute the selected compensator mathematical algorithm. The DCDT will use the default values as defined in Table 2 of the Default Values page. It is important for you to understand that this delay will not impact the calculated digital compensator coefficients, but it will have an impact on the overall system loop gain (closed-loop) phase margin.
  • Gate Drive Delay: This is the delay associated with the hardware gate-driver + MOSFET delays, (see the section on the graphical user interface, or GUI, default values). It is important for you to understand that this delay will not have an impact on the calculated digital compensator coefficients, but it will impact the overall system loop gain (closed-loop) phase margin.
  • Control Output Min/Max: These are integer values that will be used as the absolute max/min clamping limits for the compensator output. This value clamps the value written to the target register and will have no effects on the internal compensator computations.
  • Load Defaults: This button option will load the DCDT default values for the selected compensator (see the section on GUI default values).
  • Use Radian Per Second: Enabling this option allows you to input the location of poles and zeros using radians per second (Rad/sec) instead of using Hertz (Hz). It should be noted that no other parameters or bode plots would be represented in radians per second.
  • Enable Frequency Warp: This feature will enable each of the pole/zero frequencies to be Pre-Warped to ensure correct placement when mapped in the s-plane and bounded by the Nyquist frequency (FNyquist = Sampling Frequency /2).
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