PIC10F2XX, PIC12F5XX, PIC16F5XX Limitations
  • PIC16F505, PIC12F509, PIC12F508, PIC10F206, PIC10F204, PIC10F202, and PIC10F200.
  • PIC16F506, PIC12F510, PIC10F222, and PIC10F220.
  • PIC16F526 and PIC12F519.
  • PIC16F527.
  • PIC16F570.

Headers are required for debugging when using these devices. See the “Processor Extension Pak and Debug Header Specification” for details. Header limitations are as follows:

  • General Debug Limitations.
  • General Programming Limitations.
  • General Device-ME2/ICE/ICD Limitations.
  • You cannot single step through an interrupt. Due to hardware restrictions, the debugger/emulator cannot jump to the interrupt vector memory location in Single Step mode.
  • TRISIO and OPTION_REG available in Watch window but not accessible. TRISIO and OPTION_REG are available in the Watch window SFR list, but neither is accessible and will always show a value of 0.
  • Program memory standard Flash. Program memory not enhanced Flash. You cannot program in Low Voltage mode (Vdd < 4.5 V.) See device programming specification, for more information.

Freeze on Halt Limitations

  • Freeze on Halt is not supported.

PIC16F505 Only

  • MPLAB hardware debuggers do not display correct values for TRISC in the SFR window since this SFR is not addressable.

PIC16F570 Only

  • For PIC16F570 (AC244062), there is no debug visibility into GPR banks 4, 5, 6 and 7, although user access to these banks works.
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