PIC16F690 Family Limitations

Headers are required for debugging when using these devices. See the “Processor Extension Pak and Debug Header Specification” for details. Header limitations are as follows:

  • General Debug Limitations
  • General Programming Limitations
  • General Device-ME2/ICE/ICD Limitations
  • You cannot single step through an interrupt. Due to hardware restrictions, the debugger or emulator cannot jump to the interrupt vector memory location in Single Step mode.
  • You cannot erase ID memory at Vdd < 4.5 V. At Vdd < 4.5 V, the part cannot be bulk erased, so it has to be row erased. Row erase can be used on program memory but not on configuration memory (where user ID resides).
  • PIC16F690-ICD Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) Issues: Both the production devices and ICD versions of the devices have the same EUSART issues. Please refer to errata DS80243 for more information and workarounds.
  • Program memory standard Flash. Program memory not enhanced Flash. You cannot program in Low Voltage mode (Vdd < 4.5 V.) See device programming specification for more information.
  • BF is cleared when SSPBUF is interrogated by software. Above 16 MHz, in External Oscillator (EC) mode, a Reset executes the first few instructions instead of only one instruction. The workaround is to add three NOPs at the reset vector.

Freeze on Halt Limitations

  • Timer0 will not freeze using the internal clock.
  • CMOUTx pins do not freeze, status bits and interrupt flags do freeze.
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